744 lines
28 KiB
C
744 lines
28 KiB
C
/*!
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*******************************************************************************
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**
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** \file gh_timer.h
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**
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** \brief TIMER.
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**
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** Copyright: 2012 - 2013 (C) GoKe Microelectronics ShangHai Branch
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**
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** \attention THIS SAMPLE CODE IS PROVIDED AS IS. GOKE MICROELECTRONICS
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** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR
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** OMMISSIONS.
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**
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** \note Do not modify this file as it is generated automatically.
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**
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******************************************************************************/
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#ifndef _GH_TIMER_H
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#define _GH_TIMER_H
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#ifdef __LINUX__
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#include "reg4linux.h"
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#else
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#define FIO_ADDRESS(block,address) (address)
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#define FIO_MOFFSET(block,moffset) (moffset)
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#endif
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#ifndef __LINUX__
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#include "gtypes.h" /* global type definitions */
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#include "gh_lib_cfg.h" /* configuration */
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#endif
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#define GH_TIMER_ENABLE_DEBUG_PRINT 0
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#ifdef __LINUX__
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#define GH_TIMER_DEBUG_PRINT_FUNCTION printk
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#else
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#define GH_TIMER_DEBUG_PRINT_FUNCTION printf
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#endif
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#ifndef __LINUX__
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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#include <stdio.h>
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#endif
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#endif
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/* check configuration */
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#ifndef GH_INLINE_LEVEL
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#error "GH_INLINE_LEVEL is not defined!"
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#endif
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#if GH_INLINE_LEVEL > 2
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#error "GH_INLINE_LEVEL must be set 0, 1 or 2!"
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#endif
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#ifndef GH_INLINE
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#error "GH_INLINE is not defined!"
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#endif
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/* disable inlining for debugging */
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#ifdef DEBUG
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#undef GH_INLINE_LEVEL
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#define GH_INLINE_LEVEL 0
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#endif
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/*----------------------------------------------------------------------------*/
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/* registers */
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/*----------------------------------------------------------------------------*/
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#define REG_TIMER_T1CNTNSTS FIO_ADDRESS(TIMER,0xA0000000) /* read/write */
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#define REG_TIMER_T1MATCH1 FIO_ADDRESS(TIMER,0xA0000004) /* read/write */
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#define REG_TIMER_T1MATCH2 FIO_ADDRESS(TIMER,0xA0000008) /* read/write */
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#define REG_TIMER_CONTROL FIO_ADDRESS(TIMER,0xA000000C) /* read/write */
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#define REG_TIMER_T2CNTNSTS FIO_ADDRESS(TIMER,0xA0000014) /* read/write */
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#define REG_TIMER_T2MATCH1 FIO_ADDRESS(TIMER,0xA0000018) /* read/write */
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#define REG_TIMER_T2MATCH2 FIO_ADDRESS(TIMER,0xA000001C) /* read/write */
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#define REG_TIMER_T3CNTNSTS FIO_ADDRESS(TIMER,0xA0000020) /* read/write */
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#define REG_TIMER_T3MATCH1 FIO_ADDRESS(TIMER,0xA0000024) /* read/write */
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#define REG_TIMER_T3MATCH2 FIO_ADDRESS(TIMER,0xA0000028) /* read/write */
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#define REG_TIMER_T1RELOADN FIO_ADDRESS(TIMER,0xA0000030) /* read/write */
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#define REG_TIMER_T2RELOADN FIO_ADDRESS(TIMER,0xA0000034) /* read/write */
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#define REG_TIMER_T3RELOADN FIO_ADDRESS(TIMER,0xA0000038) /* read/write */
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/*----------------------------------------------------------------------------*/
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/* bit group structures */
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/*----------------------------------------------------------------------------*/
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typedef union { /* TIMER_Control */
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U32 all;
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struct {
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U32 clksel3 : 1;
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U32 clksel2 : 1;
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U32 clksel1 : 1;
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U32 : 1;
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U32 of3 : 1;
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U32 of2 : 1;
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U32 of1 : 1;
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U32 : 1;
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U32 enable3 : 1;
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U32 enable2 : 1;
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U32 enable1 : 1;
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U32 : 21;
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} bitc;
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} GH_TIMER_CONTROL_S;
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/*----------------------------------------------------------------------------*/
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/* mirror variables */
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/*----------------------------------------------------------------------------*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*----------------------------------------------------------------------------*/
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/* register TIMER_T1CntnSts (read/write) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL == 0
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/*! \brief Writes the register 'TIMER_T1CntnSts'. */
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void GH_TIMER_set_T1CntnSts(U32 data);
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/*! \brief Reads the register 'TIMER_T1CntnSts'. */
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U32 GH_TIMER_get_T1CntnSts(void);
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#else /* GH_INLINE_LEVEL == 0 */
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GH_INLINE void GH_TIMER_set_T1CntnSts(U32 data)
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{
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*(volatile U32 *)REG_TIMER_T1CNTNSTS = data;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_T1CntnSts] <-- 0x%08x\n",
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REG_TIMER_T1CNTNSTS,data,data);
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#endif
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}
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GH_INLINE U32 GH_TIMER_get_T1CntnSts(void)
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{
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U32 value = (*(volatile U32 *)REG_TIMER_T1CNTNSTS);
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_T1CntnSts] --> 0x%08x\n",
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REG_TIMER_T1CNTNSTS,value);
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#endif
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return value;
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}
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#endif /* GH_INLINE_LEVEL == 0 */
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/*----------------------------------------------------------------------------*/
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/* register TIMER_T1Match1 (read/write) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL == 0
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/*! \brief Writes the register 'TIMER_T1Match1'. */
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void GH_TIMER_set_T1Match1(U32 data);
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/*! \brief Reads the register 'TIMER_T1Match1'. */
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U32 GH_TIMER_get_T1Match1(void);
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#else /* GH_INLINE_LEVEL == 0 */
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GH_INLINE void GH_TIMER_set_T1Match1(U32 data)
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{
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*(volatile U32 *)REG_TIMER_T1MATCH1 = data;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_T1Match1] <-- 0x%08x\n",
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REG_TIMER_T1MATCH1,data,data);
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#endif
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}
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GH_INLINE U32 GH_TIMER_get_T1Match1(void)
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{
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U32 value = (*(volatile U32 *)REG_TIMER_T1MATCH1);
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_T1Match1] --> 0x%08x\n",
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REG_TIMER_T1MATCH1,value);
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#endif
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return value;
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}
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#endif /* GH_INLINE_LEVEL == 0 */
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/*----------------------------------------------------------------------------*/
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/* register TIMER_T1Match2 (read/write) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL == 0
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/*! \brief Writes the register 'TIMER_T1Match2'. */
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void GH_TIMER_set_T1Match2(U32 data);
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/*! \brief Reads the register 'TIMER_T1Match2'. */
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U32 GH_TIMER_get_T1Match2(void);
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#else /* GH_INLINE_LEVEL == 0 */
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GH_INLINE void GH_TIMER_set_T1Match2(U32 data)
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{
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*(volatile U32 *)REG_TIMER_T1MATCH2 = data;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_T1Match2] <-- 0x%08x\n",
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REG_TIMER_T1MATCH2,data,data);
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#endif
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}
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GH_INLINE U32 GH_TIMER_get_T1Match2(void)
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{
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U32 value = (*(volatile U32 *)REG_TIMER_T1MATCH2);
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_T1Match2] --> 0x%08x\n",
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REG_TIMER_T1MATCH2,value);
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#endif
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return value;
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}
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#endif /* GH_INLINE_LEVEL == 0 */
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/*----------------------------------------------------------------------------*/
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/* register TIMER_Control (read/write) */
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/*----------------------------------------------------------------------------*/
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#if GH_INLINE_LEVEL == 0
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/*! \brief Writes the register 'TIMER_Control'. */
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void GH_TIMER_set_Control(U32 data);
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/*! \brief Reads the register 'TIMER_Control'. */
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U32 GH_TIMER_get_Control(void);
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/*! \brief Writes the bit group 'ClkSel3' of register 'TIMER_Control'. */
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void GH_TIMER_set_Control_ClkSel3(U8 data);
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/*! \brief Reads the bit group 'ClkSel3' of register 'TIMER_Control'. */
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U8 GH_TIMER_get_Control_ClkSel3(void);
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/*! \brief Writes the bit group 'ClkSel2' of register 'TIMER_Control'. */
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void GH_TIMER_set_Control_ClkSel2(U8 data);
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/*! \brief Reads the bit group 'ClkSel2' of register 'TIMER_Control'. */
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U8 GH_TIMER_get_Control_ClkSel2(void);
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/*! \brief Writes the bit group 'ClkSel1' of register 'TIMER_Control'. */
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void GH_TIMER_set_Control_ClkSel1(U8 data);
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/*! \brief Reads the bit group 'ClkSel1' of register 'TIMER_Control'. */
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U8 GH_TIMER_get_Control_ClkSel1(void);
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/*! \brief Writes the bit group 'OF3' of register 'TIMER_Control'. */
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void GH_TIMER_set_Control_OF3(U8 data);
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/*! \brief Reads the bit group 'OF3' of register 'TIMER_Control'. */
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U8 GH_TIMER_get_Control_OF3(void);
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/*! \brief Writes the bit group 'OF2' of register 'TIMER_Control'. */
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void GH_TIMER_set_Control_OF2(U8 data);
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/*! \brief Reads the bit group 'OF2' of register 'TIMER_Control'. */
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U8 GH_TIMER_get_Control_OF2(void);
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/*! \brief Writes the bit group 'OF1' of register 'TIMER_Control'. */
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void GH_TIMER_set_Control_OF1(U8 data);
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/*! \brief Reads the bit group 'OF1' of register 'TIMER_Control'. */
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U8 GH_TIMER_get_Control_OF1(void);
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/*! \brief Writes the bit group 'Enable3' of register 'TIMER_Control'. */
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void GH_TIMER_set_Control_Enable3(U8 data);
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/*! \brief Reads the bit group 'Enable3' of register 'TIMER_Control'. */
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U8 GH_TIMER_get_Control_Enable3(void);
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/*! \brief Writes the bit group 'Enable2' of register 'TIMER_Control'. */
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void GH_TIMER_set_Control_Enable2(U8 data);
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/*! \brief Reads the bit group 'Enable2' of register 'TIMER_Control'. */
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U8 GH_TIMER_get_Control_Enable2(void);
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/*! \brief Writes the bit group 'Enable1' of register 'TIMER_Control'. */
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void GH_TIMER_set_Control_Enable1(U8 data);
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/*! \brief Reads the bit group 'Enable1' of register 'TIMER_Control'. */
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U8 GH_TIMER_get_Control_Enable1(void);
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#else /* GH_INLINE_LEVEL == 0 */
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GH_INLINE void GH_TIMER_set_Control(U32 data)
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{
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*(volatile U32 *)REG_TIMER_CONTROL = data;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_Control] <-- 0x%08x\n",
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REG_TIMER_CONTROL,data,data);
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#endif
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}
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GH_INLINE U32 GH_TIMER_get_Control(void)
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{
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL);
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_Control] --> 0x%08x\n",
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REG_TIMER_CONTROL,value);
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#endif
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return value;
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}
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GH_INLINE void GH_TIMER_set_Control_ClkSel3(U8 data)
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{
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GH_TIMER_CONTROL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL;
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d.bitc.clksel3 = data;
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*(volatile U32 *)REG_TIMER_CONTROL = d.all;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_Control_ClkSel3] <-- 0x%08x\n",
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REG_TIMER_CONTROL,d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_TIMER_get_Control_ClkSel3(void)
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{
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GH_TIMER_CONTROL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL);
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tmp_value.all = value;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_Control_ClkSel3] --> 0x%08x\n",
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REG_TIMER_CONTROL,value);
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#endif
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return tmp_value.bitc.clksel3;
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}
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GH_INLINE void GH_TIMER_set_Control_ClkSel2(U8 data)
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{
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GH_TIMER_CONTROL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL;
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d.bitc.clksel2 = data;
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*(volatile U32 *)REG_TIMER_CONTROL = d.all;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_Control_ClkSel2] <-- 0x%08x\n",
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REG_TIMER_CONTROL,d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_TIMER_get_Control_ClkSel2(void)
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{
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GH_TIMER_CONTROL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL);
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tmp_value.all = value;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_Control_ClkSel2] --> 0x%08x\n",
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REG_TIMER_CONTROL,value);
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#endif
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return tmp_value.bitc.clksel2;
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}
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GH_INLINE void GH_TIMER_set_Control_ClkSel1(U8 data)
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{
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GH_TIMER_CONTROL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL;
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d.bitc.clksel1 = data;
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*(volatile U32 *)REG_TIMER_CONTROL = d.all;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_Control_ClkSel1] <-- 0x%08x\n",
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REG_TIMER_CONTROL,d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_TIMER_get_Control_ClkSel1(void)
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{
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GH_TIMER_CONTROL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL);
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tmp_value.all = value;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_Control_ClkSel1] --> 0x%08x\n",
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REG_TIMER_CONTROL,value);
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#endif
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return tmp_value.bitc.clksel1;
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}
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GH_INLINE void GH_TIMER_set_Control_OF3(U8 data)
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{
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GH_TIMER_CONTROL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL;
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d.bitc.of3 = data;
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*(volatile U32 *)REG_TIMER_CONTROL = d.all;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_Control_OF3] <-- 0x%08x\n",
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REG_TIMER_CONTROL,d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_TIMER_get_Control_OF3(void)
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{
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GH_TIMER_CONTROL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL);
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tmp_value.all = value;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_Control_OF3] --> 0x%08x\n",
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REG_TIMER_CONTROL,value);
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#endif
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return tmp_value.bitc.of3;
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}
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GH_INLINE void GH_TIMER_set_Control_OF2(U8 data)
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{
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GH_TIMER_CONTROL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL;
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d.bitc.of2 = data;
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*(volatile U32 *)REG_TIMER_CONTROL = d.all;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_Control_OF2] <-- 0x%08x\n",
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REG_TIMER_CONTROL,d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_TIMER_get_Control_OF2(void)
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{
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GH_TIMER_CONTROL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL);
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tmp_value.all = value;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_Control_OF2] --> 0x%08x\n",
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REG_TIMER_CONTROL,value);
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#endif
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return tmp_value.bitc.of2;
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}
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GH_INLINE void GH_TIMER_set_Control_OF1(U8 data)
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{
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GH_TIMER_CONTROL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL;
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d.bitc.of1 = data;
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*(volatile U32 *)REG_TIMER_CONTROL = d.all;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_Control_OF1] <-- 0x%08x\n",
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REG_TIMER_CONTROL,d.all,d.all);
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#endif
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}
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GH_INLINE U8 GH_TIMER_get_Control_OF1(void)
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{
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GH_TIMER_CONTROL_S tmp_value;
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U32 value = (*(volatile U32 *)REG_TIMER_CONTROL);
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tmp_value.all = value;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_Control_OF1] --> 0x%08x\n",
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REG_TIMER_CONTROL,value);
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#endif
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return tmp_value.bitc.of1;
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}
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GH_INLINE void GH_TIMER_set_Control_Enable3(U8 data)
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{
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GH_TIMER_CONTROL_S d;
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d.all = *(volatile U32 *)REG_TIMER_CONTROL;
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d.bitc.enable3 = data;
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*(volatile U32 *)REG_TIMER_CONTROL = d.all;
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#if GH_TIMER_ENABLE_DEBUG_PRINT
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GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_Control_Enable3] <-- 0x%08x\n",
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REG_TIMER_CONTROL,d.all,d.all);
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#endif
|
|
}
|
|
GH_INLINE U8 GH_TIMER_get_Control_Enable3(void)
|
|
{
|
|
GH_TIMER_CONTROL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_TIMER_CONTROL);
|
|
|
|
tmp_value.all = value;
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_Control_Enable3] --> 0x%08x\n",
|
|
REG_TIMER_CONTROL,value);
|
|
#endif
|
|
return tmp_value.bitc.enable3;
|
|
}
|
|
GH_INLINE void GH_TIMER_set_Control_Enable2(U8 data)
|
|
{
|
|
GH_TIMER_CONTROL_S d;
|
|
d.all = *(volatile U32 *)REG_TIMER_CONTROL;
|
|
d.bitc.enable2 = data;
|
|
*(volatile U32 *)REG_TIMER_CONTROL = d.all;
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_Control_Enable2] <-- 0x%08x\n",
|
|
REG_TIMER_CONTROL,d.all,d.all);
|
|
#endif
|
|
}
|
|
GH_INLINE U8 GH_TIMER_get_Control_Enable2(void)
|
|
{
|
|
GH_TIMER_CONTROL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_TIMER_CONTROL);
|
|
|
|
tmp_value.all = value;
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_Control_Enable2] --> 0x%08x\n",
|
|
REG_TIMER_CONTROL,value);
|
|
#endif
|
|
return tmp_value.bitc.enable2;
|
|
}
|
|
GH_INLINE void GH_TIMER_set_Control_Enable1(U8 data)
|
|
{
|
|
GH_TIMER_CONTROL_S d;
|
|
d.all = *(volatile U32 *)REG_TIMER_CONTROL;
|
|
d.bitc.enable1 = data;
|
|
*(volatile U32 *)REG_TIMER_CONTROL = d.all;
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_Control_Enable1] <-- 0x%08x\n",
|
|
REG_TIMER_CONTROL,d.all,d.all);
|
|
#endif
|
|
}
|
|
GH_INLINE U8 GH_TIMER_get_Control_Enable1(void)
|
|
{
|
|
GH_TIMER_CONTROL_S tmp_value;
|
|
U32 value = (*(volatile U32 *)REG_TIMER_CONTROL);
|
|
|
|
tmp_value.all = value;
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_Control_Enable1] --> 0x%08x\n",
|
|
REG_TIMER_CONTROL,value);
|
|
#endif
|
|
return tmp_value.bitc.enable1;
|
|
}
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* register TIMER_T2CntnSts (read/write) */
|
|
/*----------------------------------------------------------------------------*/
|
|
#if GH_INLINE_LEVEL == 0
|
|
/*! \brief Writes the register 'TIMER_T2CntnSts'. */
|
|
void GH_TIMER_set_T2CntnSts(U32 data);
|
|
/*! \brief Reads the register 'TIMER_T2CntnSts'. */
|
|
U32 GH_TIMER_get_T2CntnSts(void);
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
|
GH_INLINE void GH_TIMER_set_T2CntnSts(U32 data)
|
|
{
|
|
*(volatile U32 *)REG_TIMER_T2CNTNSTS = data;
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_T2CntnSts] <-- 0x%08x\n",
|
|
REG_TIMER_T2CNTNSTS,data,data);
|
|
#endif
|
|
}
|
|
GH_INLINE U32 GH_TIMER_get_T2CntnSts(void)
|
|
{
|
|
U32 value = (*(volatile U32 *)REG_TIMER_T2CNTNSTS);
|
|
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_T2CntnSts] --> 0x%08x\n",
|
|
REG_TIMER_T2CNTNSTS,value);
|
|
#endif
|
|
return value;
|
|
}
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* register TIMER_T2Match1 (read/write) */
|
|
/*----------------------------------------------------------------------------*/
|
|
#if GH_INLINE_LEVEL == 0
|
|
/*! \brief Writes the register 'TIMER_T2Match1'. */
|
|
void GH_TIMER_set_T2Match1(U32 data);
|
|
/*! \brief Reads the register 'TIMER_T2Match1'. */
|
|
U32 GH_TIMER_get_T2Match1(void);
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
|
GH_INLINE void GH_TIMER_set_T2Match1(U32 data)
|
|
{
|
|
*(volatile U32 *)REG_TIMER_T2MATCH1 = data;
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_T2Match1] <-- 0x%08x\n",
|
|
REG_TIMER_T2MATCH1,data,data);
|
|
#endif
|
|
}
|
|
GH_INLINE U32 GH_TIMER_get_T2Match1(void)
|
|
{
|
|
U32 value = (*(volatile U32 *)REG_TIMER_T2MATCH1);
|
|
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_T2Match1] --> 0x%08x\n",
|
|
REG_TIMER_T2MATCH1,value);
|
|
#endif
|
|
return value;
|
|
}
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* register TIMER_T2Match2 (read/write) */
|
|
/*----------------------------------------------------------------------------*/
|
|
#if GH_INLINE_LEVEL == 0
|
|
/*! \brief Writes the register 'TIMER_T2Match2'. */
|
|
void GH_TIMER_set_T2Match2(U32 data);
|
|
/*! \brief Reads the register 'TIMER_T2Match2'. */
|
|
U32 GH_TIMER_get_T2Match2(void);
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
|
GH_INLINE void GH_TIMER_set_T2Match2(U32 data)
|
|
{
|
|
*(volatile U32 *)REG_TIMER_T2MATCH2 = data;
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_T2Match2] <-- 0x%08x\n",
|
|
REG_TIMER_T2MATCH2,data,data);
|
|
#endif
|
|
}
|
|
GH_INLINE U32 GH_TIMER_get_T2Match2(void)
|
|
{
|
|
U32 value = (*(volatile U32 *)REG_TIMER_T2MATCH2);
|
|
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_T2Match2] --> 0x%08x\n",
|
|
REG_TIMER_T2MATCH2,value);
|
|
#endif
|
|
return value;
|
|
}
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* register TIMER_T3CntnSts (read/write) */
|
|
/*----------------------------------------------------------------------------*/
|
|
#if GH_INLINE_LEVEL == 0
|
|
/*! \brief Writes the register 'TIMER_T3CntnSts'. */
|
|
void GH_TIMER_set_T3CntnSts(U32 data);
|
|
/*! \brief Reads the register 'TIMER_T3CntnSts'. */
|
|
U32 GH_TIMER_get_T3CntnSts(void);
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
|
GH_INLINE void GH_TIMER_set_T3CntnSts(U32 data)
|
|
{
|
|
*(volatile U32 *)REG_TIMER_T3CNTNSTS = data;
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_T3CntnSts] <-- 0x%08x\n",
|
|
REG_TIMER_T3CNTNSTS,data,data);
|
|
#endif
|
|
}
|
|
GH_INLINE U32 GH_TIMER_get_T3CntnSts(void)
|
|
{
|
|
U32 value = (*(volatile U32 *)REG_TIMER_T3CNTNSTS);
|
|
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_T3CntnSts] --> 0x%08x\n",
|
|
REG_TIMER_T3CNTNSTS,value);
|
|
#endif
|
|
return value;
|
|
}
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* register TIMER_T3Match1 (read/write) */
|
|
/*----------------------------------------------------------------------------*/
|
|
#if GH_INLINE_LEVEL == 0
|
|
/*! \brief Writes the register 'TIMER_T3Match1'. */
|
|
void GH_TIMER_set_T3Match1(U32 data);
|
|
/*! \brief Reads the register 'TIMER_T3Match1'. */
|
|
U32 GH_TIMER_get_T3Match1(void);
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
|
GH_INLINE void GH_TIMER_set_T3Match1(U32 data)
|
|
{
|
|
*(volatile U32 *)REG_TIMER_T3MATCH1 = data;
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_T3Match1] <-- 0x%08x\n",
|
|
REG_TIMER_T3MATCH1,data,data);
|
|
#endif
|
|
}
|
|
GH_INLINE U32 GH_TIMER_get_T3Match1(void)
|
|
{
|
|
U32 value = (*(volatile U32 *)REG_TIMER_T3MATCH1);
|
|
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_T3Match1] --> 0x%08x\n",
|
|
REG_TIMER_T3MATCH1,value);
|
|
#endif
|
|
return value;
|
|
}
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* register TIMER_T3Match2 (read/write) */
|
|
/*----------------------------------------------------------------------------*/
|
|
#if GH_INLINE_LEVEL == 0
|
|
/*! \brief Writes the register 'TIMER_T3Match2'. */
|
|
void GH_TIMER_set_T3Match2(U32 data);
|
|
/*! \brief Reads the register 'TIMER_T3Match2'. */
|
|
U32 GH_TIMER_get_T3Match2(void);
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
|
GH_INLINE void GH_TIMER_set_T3Match2(U32 data)
|
|
{
|
|
*(volatile U32 *)REG_TIMER_T3MATCH2 = data;
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_T3Match2] <-- 0x%08x\n",
|
|
REG_TIMER_T3MATCH2,data,data);
|
|
#endif
|
|
}
|
|
GH_INLINE U32 GH_TIMER_get_T3Match2(void)
|
|
{
|
|
U32 value = (*(volatile U32 *)REG_TIMER_T3MATCH2);
|
|
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_T3Match2] --> 0x%08x\n",
|
|
REG_TIMER_T3MATCH2,value);
|
|
#endif
|
|
return value;
|
|
}
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* register TIMER_T1Reloadn (read/write) */
|
|
/*----------------------------------------------------------------------------*/
|
|
#if GH_INLINE_LEVEL == 0
|
|
/*! \brief Writes the register 'TIMER_T1Reloadn'. */
|
|
void GH_TIMER_set_T1Reloadn(U32 data);
|
|
/*! \brief Reads the register 'TIMER_T1Reloadn'. */
|
|
U32 GH_TIMER_get_T1Reloadn(void);
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
|
GH_INLINE void GH_TIMER_set_T1Reloadn(U32 data)
|
|
{
|
|
*(volatile U32 *)REG_TIMER_T1RELOADN = data;
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_T1Reloadn] <-- 0x%08x\n",
|
|
REG_TIMER_T1RELOADN,data,data);
|
|
#endif
|
|
}
|
|
GH_INLINE U32 GH_TIMER_get_T1Reloadn(void)
|
|
{
|
|
U32 value = (*(volatile U32 *)REG_TIMER_T1RELOADN);
|
|
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_T1Reloadn] --> 0x%08x\n",
|
|
REG_TIMER_T1RELOADN,value);
|
|
#endif
|
|
return value;
|
|
}
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* register TIMER_T2Reloadn (read/write) */
|
|
/*----------------------------------------------------------------------------*/
|
|
#if GH_INLINE_LEVEL == 0
|
|
/*! \brief Writes the register 'TIMER_T2Reloadn'. */
|
|
void GH_TIMER_set_T2Reloadn(U32 data);
|
|
/*! \brief Reads the register 'TIMER_T2Reloadn'. */
|
|
U32 GH_TIMER_get_T2Reloadn(void);
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
|
GH_INLINE void GH_TIMER_set_T2Reloadn(U32 data)
|
|
{
|
|
*(volatile U32 *)REG_TIMER_T2RELOADN = data;
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_T2Reloadn] <-- 0x%08x\n",
|
|
REG_TIMER_T2RELOADN,data,data);
|
|
#endif
|
|
}
|
|
GH_INLINE U32 GH_TIMER_get_T2Reloadn(void)
|
|
{
|
|
U32 value = (*(volatile U32 *)REG_TIMER_T2RELOADN);
|
|
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_T2Reloadn] --> 0x%08x\n",
|
|
REG_TIMER_T2RELOADN,value);
|
|
#endif
|
|
return value;
|
|
}
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* register TIMER_T3Reloadn (read/write) */
|
|
/*----------------------------------------------------------------------------*/
|
|
#if GH_INLINE_LEVEL == 0
|
|
/*! \brief Writes the register 'TIMER_T3Reloadn'. */
|
|
void GH_TIMER_set_T3Reloadn(U32 data);
|
|
/*! \brief Reads the register 'TIMER_T3Reloadn'. */
|
|
U32 GH_TIMER_get_T3Reloadn(void);
|
|
#else /* GH_INLINE_LEVEL == 0 */
|
|
GH_INLINE void GH_TIMER_set_T3Reloadn(U32 data)
|
|
{
|
|
*(volatile U32 *)REG_TIMER_T3RELOADN = data;
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "WRREG(0x%08x,0x%08x); \\\\ [GH_TIMER_set_T3Reloadn] <-- 0x%08x\n",
|
|
REG_TIMER_T3RELOADN,data,data);
|
|
#endif
|
|
}
|
|
GH_INLINE U32 GH_TIMER_get_T3Reloadn(void)
|
|
{
|
|
U32 value = (*(volatile U32 *)REG_TIMER_T3RELOADN);
|
|
|
|
#if GH_TIMER_ENABLE_DEBUG_PRINT
|
|
GH_TIMER_DEBUG_PRINT_FUNCTION( "value = RDREG(0x%08x); \\\\ [GH_TIMER_get_T3Reloadn] --> 0x%08x\n",
|
|
REG_TIMER_T3RELOADN,value);
|
|
#endif
|
|
return value;
|
|
}
|
|
#endif /* GH_INLINE_LEVEL == 0 */
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* init function */
|
|
/*----------------------------------------------------------------------------*/
|
|
/*! \brief Initialises the registers and mirror variables. */
|
|
void GH_TIMER_init(void);
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _GH_TIMER_H */
|
|
|
|
/*----------------------------------------------------------------------------*/
|
|
/* end of file */
|
|
/*----------------------------------------------------------------------------*/
|
|
|