563 lines
14 KiB
C
563 lines
14 KiB
C
/*
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* Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-01-14 wangyq the first version
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*/
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#include <rthw.h>
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#include <rtdevice.h>
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#include "board.h"
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#include "drv_gpio.h"
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#include <ald_cmu.h>
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#include <ald_gpio.h>
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#ifdef RT_USING_PIN
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#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index}
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#define __ES32F0_PIN_DEFAULT {-1, 0, 0}
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/* ES32F0 GPIO driver */
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struct pin_index
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{
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int index;
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GPIO_TypeDef *gpio;
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uint32_t pin;
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};
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static const struct pin_index pins[] =
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{
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN(2, C, 13),
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__ES32F0_PIN(3, C, 14),
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__ES32F0_PIN(4, C, 15),
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__ES32F0_PIN(5, H, 0),
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__ES32F0_PIN(6, H, 1),
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN(8, C, 0),
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__ES32F0_PIN(9, C, 1),
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__ES32F0_PIN(10, C, 2),
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__ES32F0_PIN(11, C, 3),
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__ES32F0_PIN(12, H, 3),
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__ES32F0_PIN(13, H, 4),
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__ES32F0_PIN(14, A, 0),
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__ES32F0_PIN(15, A, 1),
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__ES32F0_PIN(16, A, 2),
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__ES32F0_PIN(17, A, 3),
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__ES32F0_PIN(18, F, 0),
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__ES32F0_PIN(19, F, 1),
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__ES32F0_PIN(20, A, 4),
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__ES32F0_PIN(21, A, 5),
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__ES32F0_PIN(22, A, 6),
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__ES32F0_PIN(23, A, 7),
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__ES32F0_PIN(24, C, 4),
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__ES32F0_PIN(25, C, 5),
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__ES32F0_PIN(26, B, 0),
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__ES32F0_PIN(27, B, 1),
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__ES32F0_PIN(28, B, 2),
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__ES32F0_PIN(29, B, 10),
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__ES32F0_PIN(30, B, 11),
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN(33, B, 12),
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__ES32F0_PIN(34, B, 13),
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__ES32F0_PIN(35, B, 14),
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__ES32F0_PIN(36, B, 15),
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__ES32F0_PIN(37, C, 6),
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__ES32F0_PIN(38, C, 7),
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__ES32F0_PIN(39, C, 8),
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN(46, A, 13),
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN(49, A, 14),
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__ES32F0_PIN(50, A, 15),
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__ES32F0_PIN(51, C, 10),
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__ES32F0_PIN(52, C, 11),
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__ES32F0_PIN(53, C, 12),
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__ES32F0_PIN(54, D, 2),
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__ES32F0_PIN(55, B, 3),
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__ES32F0_PIN(56, B, 4),
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__ES32F0_PIN(57, B, 5),
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__ES32F0_PIN(58, B, 6),
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__ES32F0_PIN(59, B, 7),
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__ES32F0_PIN(60, H, 2),
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__ES32F0_PIN(61, B, 8),
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__ES32F0_PIN(62, B, 9),
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__ES32F0_PIN_DEFAULT,
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__ES32F0_PIN_DEFAULT,
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};
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struct pin_irq_map
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{
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rt_uint16_t pinbit;
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IRQn_Type irqno;
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};
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static const struct pin_irq_map pin_irq_map[] =
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{
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{GPIO_PIN_0, EXTI0_IRQn},
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{GPIO_PIN_1, EXTI1_IRQn},
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{GPIO_PIN_2, EXTI2_IRQn},
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{GPIO_PIN_3, EXTI3_IRQn},
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{GPIO_PIN_4, EXTI4_IRQn},
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{GPIO_PIN_5, EXTI5_IRQn},
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{GPIO_PIN_6, EXTI6_IRQn},
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{GPIO_PIN_7, EXTI7_IRQn},
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{GPIO_PIN_8, EXTI8_IRQn},
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{GPIO_PIN_9, EXTI9_IRQn},
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{GPIO_PIN_10, EXTI10_IRQn},
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{GPIO_PIN_11, EXTI11_IRQn},
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{GPIO_PIN_12, EXTI12_IRQn},
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{GPIO_PIN_13, EXTI13_IRQn},
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{GPIO_PIN_14, EXTI14_IRQn},
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{GPIO_PIN_15, EXTI15_IRQn},
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};
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struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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{ -1, 0, RT_NULL, RT_NULL},
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};
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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const struct pin_index *get_pin(uint8_t pin)
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{
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const struct pin_index *index;
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if (pin < ITEM_NUM(pins))
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{
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index = &pins[pin];
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if (index->index == -1)
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index = RT_NULL;
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}
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else
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{
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index = RT_NULL;
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}
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return index;
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};
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void es32f3_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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{
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const struct pin_index *index;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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ald_gpio_write_pin(index->gpio, index->pin, value);
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}
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int es32f3_pin_read(rt_device_t dev, rt_base_t pin)
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{
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int value;
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const struct pin_index *index;
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value = PIN_LOW;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return value;
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}
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value = ald_gpio_read_pin(index->gpio, index->pin);
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return value;
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}
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void es32f3_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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const struct pin_index *index;
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gpio_init_t gpio_initstruct;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return;
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}
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/* Configure GPIO_InitStructure */
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gpio_initstruct.mode = GPIO_MODE_OUTPUT;
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gpio_initstruct.func = GPIO_FUNC_1;
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gpio_initstruct.podrv = GPIO_OUT_DRIVE_1;
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gpio_initstruct.nodrv = GPIO_OUT_DRIVE_0_1;
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gpio_initstruct.type = GPIO_TYPE_CMOS;
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gpio_initstruct.pupd = GPIO_FLOATING;
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gpio_initstruct.odos = GPIO_PUSH_PULL;
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if (mode == PIN_MODE_OUTPUT)
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{
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/* output setting */
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gpio_initstruct.mode = GPIO_MODE_OUTPUT;
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gpio_initstruct.pupd = GPIO_FLOATING;
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}
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else if (mode == PIN_MODE_INPUT)
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{
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/* input setting: not pull. */
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gpio_initstruct.mode = GPIO_MODE_INPUT;
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gpio_initstruct.pupd = GPIO_FLOATING;
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}
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else if (mode == PIN_MODE_INPUT_PULLUP)
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{
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/* input setting: pull up. */
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gpio_initstruct.mode = GPIO_MODE_INPUT;
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gpio_initstruct.pupd = GPIO_PUSH_UP;
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}
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else if (mode == PIN_MODE_INPUT_PULLDOWN)
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{
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/* input setting: pull down. */
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gpio_initstruct.mode = GPIO_MODE_INPUT;
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gpio_initstruct.pupd = GPIO_PUSH_DOWN;
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}
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else if (mode == PIN_MODE_OUTPUT_OD)
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{
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/* output setting: od. */
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gpio_initstruct.mode = GPIO_MODE_OUTPUT;
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gpio_initstruct.pupd = GPIO_FLOATING;
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gpio_initstruct.odos = GPIO_OPEN_DRAIN;
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}
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ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
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}
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rt_inline const struct pin_irq_map *get_pin_irq_map(rt_uint16_t gpio_pin)
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{
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rt_int32_t mapindex = gpio_pin & 0x00FF;
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if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_NULL;
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}
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return &pin_irq_map[mapindex];
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};
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rt_err_t es32f3_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_uint32_t mode, void (*hdr)(void *args), void *args)
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t irqindex;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return RT_ENOSYS;
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}
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/* pin no. convert to dec no. */
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for (irqindex = 0; irqindex < 16; irqindex++)
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{
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if ((0x01 << irqindex) == index->pin)
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{
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break;
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}
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}
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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pin_irq_hdr_tab[irqindex].hdr == hdr &&
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pin_irq_hdr_tab[irqindex].mode == mode &&
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pin_irq_hdr_tab[irqindex].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EBUSY;
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}
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pin_irq_hdr_tab[irqindex].pin = pin;
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pin_irq_hdr_tab[irqindex].hdr = hdr;
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pin_irq_hdr_tab[irqindex].mode = mode;
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pin_irq_hdr_tab[irqindex].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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rt_err_t es32f3_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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{
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const struct pin_index *index;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return RT_ENOSYS;
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}
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irqindex = index->pin & 0x00FF;
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_tab[irqindex].pin = -1;
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pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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pin_irq_hdr_tab[irqindex].mode = 0;
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pin_irq_hdr_tab[irqindex].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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rt_err_t es32f3_pin_irq_enable(struct rt_device *device, rt_base_t pin,
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rt_uint32_t enabled)
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{
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const struct pin_index *index;
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const struct pin_irq_map *irqmap;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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/* Configure GPIO_InitStructure & EXTI_InitStructure */
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gpio_init_t gpio_initstruct;
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exti_init_t exti_initstruct;
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exti_initstruct.filter = DISABLE;
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exti_initstruct.cks = EXTI_FILTER_CLOCK_10K;
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exti_initstruct.filter_time = 0x0;
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index = get_pin(pin);
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if (index == RT_NULL)
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{
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return RT_ENOSYS;
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}
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if (enabled == PIN_IRQ_ENABLE)
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{
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/* pin no. convert to dec no. */
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for (irqindex = 0; irqindex < 16; irqindex++)
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{
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if ((0x01 << irqindex) == index->pin)
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{
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break;
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}
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}
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if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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{
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return RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_ENOSYS;
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}
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irqmap = &pin_irq_map[irqindex];
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ald_gpio_exti_init(index->gpio, index->pin, &exti_initstruct);
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/* Configure GPIO_InitStructure */
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gpio_initstruct.mode = GPIO_MODE_INPUT;
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gpio_initstruct.func = GPIO_FUNC_1;
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switch (pin_irq_hdr_tab[irqindex].mode)
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{
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case PIN_IRQ_MODE_RISING:
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gpio_initstruct.pupd = GPIO_PUSH_DOWN;
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ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_RISING_EDGE, ENABLE);
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break;
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case PIN_IRQ_MODE_FALLING:
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gpio_initstruct.pupd = GPIO_PUSH_UP;
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ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_TRAILING_EDGE, ENABLE);
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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gpio_initstruct.pupd = GPIO_FLOATING;
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ald_gpio_exti_interrupt_config(index->pin, EXTI_TRIGGER_BOTH_EDGE, ENABLE);
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break;
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}
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ald_gpio_init(index->gpio, index->pin, &gpio_initstruct);
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NVIC_EnableIRQ(irqmap->irqno);
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rt_hw_interrupt_enable(level);
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}
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else if (enabled == PIN_IRQ_DISABLE)
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{
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irqmap = get_pin_irq_map(index->pin);
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if (irqmap == RT_NULL)
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{
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return RT_ENOSYS;
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}
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NVIC_DisableIRQ(irqmap->irqno);
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}
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else
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{
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return RT_ENOSYS;
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}
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return RT_EOK;
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}
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const static struct rt_pin_ops _es32f3_pin_ops =
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{
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es32f3_pin_mode,
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es32f3_pin_write,
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es32f3_pin_read,
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es32f3_pin_attach_irq,
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es32f3_pin_detach_irq,
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es32f3_pin_irq_enable,
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};
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int rt_hw_pin_init(void)
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{
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int result;
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ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE);
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result = rt_device_pin_register("pin", &_es32f3_pin_ops, RT_NULL);
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return result;
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}
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INIT_BOARD_EXPORT(rt_hw_pin_init);
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rt_inline void pin_irq_hdr(uint16_t GPIO_Pin)
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{
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uint16_t irqno;
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/* pin no. convert to dec no. */
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for (irqno = 0; irqno < 16; irqno++)
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{
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if ((0x01 << irqno) == GPIO_Pin)
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{
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break;
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}
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}
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if (irqno == 16)
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return;
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if (pin_irq_hdr_tab[irqno].hdr)
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{
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pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
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}
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}
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void GPIO_EXTI_Callback(uint16_t GPIO_Pin)
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{
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if (ald_gpio_exti_get_flag_status(GPIO_Pin) != RESET)
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{
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ald_gpio_exti_clear_flag_status(GPIO_Pin);
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pin_irq_hdr(GPIO_Pin);
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}
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}
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void EXTI0_Handler(void)
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{
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rt_interrupt_enter();
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GPIO_EXTI_Callback(GPIO_PIN_0);
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rt_interrupt_leave();
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}
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void EXTI1_Handler(void)
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{
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rt_interrupt_enter();
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GPIO_EXTI_Callback(GPIO_PIN_1);
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rt_interrupt_leave();
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}
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void EXTI2_Handler(void)
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{
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rt_interrupt_enter();
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GPIO_EXTI_Callback(GPIO_PIN_2);
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rt_interrupt_leave();
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}
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void EXTI3_Handler(void)
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{
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rt_interrupt_enter();
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GPIO_EXTI_Callback(GPIO_PIN_3);
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rt_interrupt_leave();
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}
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void EXTI4_Handler(void)
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{
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rt_interrupt_enter();
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GPIO_EXTI_Callback(GPIO_PIN_4);
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rt_interrupt_leave();
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}
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void EXTI5_Handler(void)
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{
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rt_interrupt_enter();
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GPIO_EXTI_Callback(GPIO_PIN_5);
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rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI6_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(GPIO_PIN_6);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI7_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(GPIO_PIN_7);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI8_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(GPIO_PIN_8);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI9_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(GPIO_PIN_9);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI10_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(GPIO_PIN_10);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI11_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(GPIO_PIN_11);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI12_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(GPIO_PIN_12);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI13_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(GPIO_PIN_13);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI14_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(GPIO_PIN_14);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
void EXTI15_Handler(void)
|
|
{
|
|
rt_interrupt_enter();
|
|
GPIO_EXTI_Callback(GPIO_PIN_15);
|
|
rt_interrupt_leave();
|
|
}
|
|
|
|
#endif
|