178 lines
3.7 KiB
C
178 lines
3.7 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-07-29 zdzn first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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#include "drv_uart.h"
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#include "drv_timer.h"
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#include "cp15.h"
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#ifdef RT_USING_SMP
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unsigned int cntfrq;
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#endif
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void rt_hw_timer_isr(int vector, void *parameter)
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{
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rt_tick_increase();
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#ifndef RT_USING_SMP
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ARM_TIMER_IRQCLR = 0;
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#else
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mask_cntv();
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__DSB();
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write_cntv_tval(cntfrq);
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__DSB();
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unmask_cntv();
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__DSB();
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#endif
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}
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int rt_hw_timer_init()
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{
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#ifndef RT_USING_SMP
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/* timer_clock = apb_clock/(pre_divider + 1) */
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ARM_TIMER_PREDIV = (250 - 1);
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ARM_TIMER_RELOAD = 0;
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ARM_TIMER_LOAD = 0;
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ARM_TIMER_IRQCLR = 0;
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ARM_TIMER_CTRL = 0;
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ARM_TIMER_RELOAD = 10000;
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ARM_TIMER_LOAD = 10000;
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/* 23-bit counter, enable interrupt, enable timer */
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ARM_TIMER_CTRL = (1 << 1) | (1 << 5) | (1 << 7);
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#else
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__DSB();
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cntfrq = 35000;
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write_cntv_tval(cntfrq);
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enable_cntv();
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__DSB();
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enable_cpu_timer_intr(rt_hw_cpu_id());
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#endif
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rt_hw_interrupt_install(IRQ_ARM_TIMER, rt_hw_timer_isr, RT_NULL, "tick");
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rt_hw_interrupt_umask(IRQ_ARM_TIMER);
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return 0;
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}
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#ifdef RT_USING_SMP
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extern void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler);
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void ipi_handler()
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{
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rt_scheduler_ipi_handler(0,RT_NULL);
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}
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#endif
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void idle_wfi(void)
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{
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asm volatile ("wfi");
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}
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void rt_hw_board_init(void)
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{
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/* initialize hardware interrupt */
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rt_hw_interrupt_init();
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rt_hw_vector_init();
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/* initialize uart */
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rt_hw_uart_init();
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/* initialize timer for os tick */
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rt_hw_timer_init();
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rt_thread_idle_sethook(idle_wfi);
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#ifdef RT_USING_CONSOLE
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/* set console device */
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif /* RT_USING_CONSOLE */
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#ifdef RT_USING_HEAP
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/* initialize memory system */
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rt_kprintf("heap: 0x%08x - 0x%08x\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
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rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
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#endif
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#ifdef RT_USING_SMP
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/* install IPI handle */
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rt_hw_ipi_handler_install(IRQ_ARM_MAILBOX, ipi_handler);
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rt_hw_interrupt_umask(IRQ_ARM_MAILBOX);
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enable_cpu_ipi_intr(0);
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#endif
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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}
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void _reset(void);
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void secondary_cpu_start(void);
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#ifdef RT_USING_SMP
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void rt_hw_secondary_cpu_up(void)
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{
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int i;
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int retry,val;
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rt_cpu_dcache_clean_flush();
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rt_cpu_icache_flush();
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/*TODO maybe, there is some bug */
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for (i = RT_CPUS_NR - 1; i>0; i-- )
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{
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rt_kprintf("boot cpu:%d\n", i);
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setup_bootstrap_addr(i, (int)_reset);
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__SEV();
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__DSB();
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__ISB();
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retry = 10;
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rt_thread_delay(RT_TICK_PER_SECOND/1000);
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do
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{
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val = CORE_MAILBOX3_CLEAR(i);
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if (val == 0)
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{
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rt_kprintf("start OK: CPU %d \n",i);
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break;
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}
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rt_thread_delay(RT_TICK_PER_SECOND);
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retry --;
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if (retry <= 0)
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{
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rt_kprintf("can't start for CPU %d \n",i);
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break;
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}
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} while (1);
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}
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__DSB();
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__SEV();
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}
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void secondary_cpu_c_start(void)
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{
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uint32_t id;
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id = rt_hw_cpu_id();
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rt_kprintf("cpu = 0x%08x\n",id);
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rt_hw_timer_init();
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rt_kprintf("cpu %d startup.\n",id);
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rt_hw_vector_init();
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enable_cpu_ipi_intr(id);
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rt_hw_spin_lock(&_cpus_lock);
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rt_system_scheduler_start();
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}
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void rt_hw_secondary_cpu_idle_exec(void)
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{
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__WFE();
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}
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#endif
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