523 lines
14 KiB
C
523 lines
14 KiB
C
/*
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* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-04-28 CDT first version
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* 2023-10-09 CDT support HC32F448
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "drv_gpio.h"
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#include "board_config.h"
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#if defined(RT_USING_PIN)
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#if defined(BSP_USING_GPIO)
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#define GPIO_PIN_INDEX(pin) ((uint8_t)((pin) & 0x0F))
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#define PIN_NUM(port, pin) (((((port) & 0x0F) << 4) | ((pin) & 0x0F)))
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#define GPIO_PORT(pin) ((uint8_t)(((pin) >> 4) & 0x0F))
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#define GPIO_PIN(pin) ((uint16_t)(0x01U << GPIO_PIN_INDEX(pin)))
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#if defined (HC32F4A0)
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#define PIN_MAX_NUM ((GPIO_PORT_I * 16) + (__CLZ(__RBIT(GPIO_PIN_13))) + 1)
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#elif defined (HC32F460)
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#define PIN_MAX_NUM ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1)
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#elif defined (HC32F448)
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#define PIN_MAX_NUM ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1)
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#elif defined (HC32F472)
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#define PIN_MAX_NUM ((GPIO_PORT_F * 16) + (__CLZ(__RBIT(GPIO_PIN_08))) + 1)
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#endif
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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#ifndef HC32_PIN_CONFIG
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#define HC32_PIN_CONFIG(pin, callback, config) \
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{ \
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.pinbit = pin, \
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.irq_callback = callback, \
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.irq_config = config, \
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}
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#endif /* HC32_PIN_CONFIG */
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static void extint0_irq_handler(void);
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static void extint1_irq_handler(void);
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static void extint2_irq_handler(void);
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static void extint3_irq_handler(void);
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static void extint4_irq_handler(void);
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static void extint5_irq_handler(void);
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static void extint6_irq_handler(void);
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static void extint7_irq_handler(void);
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static void extint8_irq_handler(void);
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static void extint9_irq_handler(void);
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static void extint10_irq_handler(void);
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static void extint11_irq_handler(void);
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static void extint12_irq_handler(void);
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static void extint13_irq_handler(void);
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static void extint14_irq_handler(void);
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static void extint15_irq_handler(void);
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static struct hc32_pin_irq_map pin_irq_map[] =
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{
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HC32_PIN_CONFIG(GPIO_PIN_00, extint0_irq_handler, EXTINT0_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_01, extint1_irq_handler, EXTINT1_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_02, extint2_irq_handler, EXTINT2_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_03, extint3_irq_handler, EXTINT3_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_04, extint4_irq_handler, EXTINT4_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_05, extint5_irq_handler, EXTINT5_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_06, extint6_irq_handler, EXTINT6_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_07, extint7_irq_handler, EXTINT7_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_08, extint8_irq_handler, EXTINT8_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_09, extint9_irq_handler, EXTINT9_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_10, extint10_irq_handler, EXTINT10_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_11, extint11_irq_handler, EXTINT11_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_12, extint12_irq_handler, EXTINT12_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_13, extint13_irq_handler, EXTINT13_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_14, extint14_irq_handler, EXTINT14_IRQ_CONFIG),
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HC32_PIN_CONFIG(GPIO_PIN_15, extint15_irq_handler, EXTINT15_IRQ_CONFIG),
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};
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struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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{-1, 0, RT_NULL, RT_NULL},
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};
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static void pin_irq_handler(rt_uint16_t pinbit)
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{
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rt_int32_t irqindex = -1;
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if (SET == EXTINT_GetExtIntStatus(pinbit))
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{
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EXTINT_ClearExtIntStatus(pinbit);
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irqindex = __CLZ(__RBIT(pinbit));
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if (pin_irq_hdr_tab[irqindex].hdr)
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{
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pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args);
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}
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}
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}
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static void extint0_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[0].pinbit);
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rt_interrupt_leave();
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}
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static void extint1_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[1].pinbit);
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rt_interrupt_leave();
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}
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static void extint2_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[2].pinbit);
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rt_interrupt_leave();
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}
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static void extint3_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[3].pinbit);
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rt_interrupt_leave();
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}
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static void extint4_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[4].pinbit);
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rt_interrupt_leave();
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}
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static void extint5_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[5].pinbit);
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rt_interrupt_leave();
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}
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static void extint6_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[6].pinbit);
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rt_interrupt_leave();
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}
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static void extint7_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[7].pinbit);
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rt_interrupt_leave();
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}
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static void extint8_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[8].pinbit);
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rt_interrupt_leave();
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}
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static void extint9_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[9].pinbit);
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rt_interrupt_leave();
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}
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static void extint10_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[10].pinbit);
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rt_interrupt_leave();
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}
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static void extint11_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[11].pinbit);
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rt_interrupt_leave();
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}
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static void extint12_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[12].pinbit);
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rt_interrupt_leave();
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}
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static void extint13_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[13].pinbit);
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rt_interrupt_leave();
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}
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static void extint14_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[14].pinbit);
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rt_interrupt_leave();
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}
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static void extint15_irq_handler(void)
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{
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rt_interrupt_enter();
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pin_irq_handler(pin_irq_map[15].pinbit);
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rt_interrupt_leave();
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}
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static void hc32_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode)
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{
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stc_gpio_init_t stcGpioInit;
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if (pin >= PIN_MAX_NUM)
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{
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return;
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}
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GPIO_StructInit(&stcGpioInit);
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switch (mode)
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{
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case PIN_MODE_OUTPUT:
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stcGpioInit.u16PinDir = PIN_DIR_OUT;
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stcGpioInit.u16PinOutputType = PIN_OUT_TYPE_CMOS;
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break;
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case PIN_MODE_INPUT:
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stcGpioInit.u16PinDir = PIN_DIR_IN;
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break;
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case PIN_MODE_INPUT_PULLUP:
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stcGpioInit.u16PinDir = PIN_DIR_IN;
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stcGpioInit.u16PullUp = PIN_PU_ON;
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break;
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case PIN_MODE_INPUT_PULLDOWN:
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stcGpioInit.u16PinDir = PIN_DIR_IN;
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stcGpioInit.u16PullUp = PIN_PU_OFF;
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#if defined (HC32F448) || defined (HC32F472)
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stcGpioInit.u16PullDown = PIN_PD_ON;
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#endif
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break;
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case PIN_MODE_OUTPUT_OD:
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stcGpioInit.u16PinDir = PIN_DIR_OUT;
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stcGpioInit.u16PinOutputType = PIN_OUT_TYPE_NMOS;
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break;
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default:
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break;
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}
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GPIO_Init(GPIO_PORT(pin), GPIO_PIN(pin), &stcGpioInit);
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}
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static void hc32_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value)
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{
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uint8_t gpio_port;
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uint16_t gpio_pin;
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if (pin < PIN_MAX_NUM)
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{
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gpio_port = GPIO_PORT(pin);
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gpio_pin = GPIO_PIN(pin);
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if (PIN_LOW == value)
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{
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GPIO_ResetPins(gpio_port, gpio_pin);
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}
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else
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{
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GPIO_SetPins(gpio_port, gpio_pin);
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}
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}
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}
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static rt_ssize_t hc32_pin_read(struct rt_device *device, rt_base_t pin)
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{
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uint8_t gpio_port;
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uint16_t gpio_pin;
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int value = PIN_LOW;
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if (pin < PIN_MAX_NUM)
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{
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gpio_port = GPIO_PORT(pin);
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gpio_pin = GPIO_PIN(pin);
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if (PIN_RESET == GPIO_ReadInputPins(gpio_port, gpio_pin))
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{
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value = PIN_LOW;
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}
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else
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{
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value = PIN_HIGH;
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}
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}
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else
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{
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return -RT_EINVAL;
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}
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return value;
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}
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static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_base_t pin,
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rt_uint8_t mode, void (*hdr)(void *args), void *args)
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{
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (pin >= PIN_MAX_NUM)
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{
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return -RT_ENOSYS;
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}
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irqindex = GPIO_PIN_INDEX(pin);
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if (irqindex >= ITEM_NUM(pin_irq_map))
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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pin_irq_hdr_tab[irqindex].hdr == hdr &&
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pin_irq_hdr_tab[irqindex].mode == mode &&
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pin_irq_hdr_tab[irqindex].args == args)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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if (pin_irq_hdr_tab[irqindex].pin != -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_EBUSY;
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}
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pin_irq_hdr_tab[irqindex].pin = pin;
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pin_irq_hdr_tab[irqindex].hdr = hdr;
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pin_irq_hdr_tab[irqindex].mode = mode;
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pin_irq_hdr_tab[irqindex].args = args;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_err_t hc32_pin_detach_irq(struct rt_device *device, rt_base_t pin)
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{
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rt_base_t level;
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rt_int32_t irqindex = -1;
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if (pin >= PIN_MAX_NUM)
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{
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return -RT_ENOSYS;
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}
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irqindex = GPIO_PIN_INDEX(pin);
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if (irqindex >= ITEM_NUM(pin_irq_map))
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{
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return -RT_ENOSYS;
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}
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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pin_irq_hdr_tab[irqindex].pin = -1;
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pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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pin_irq_hdr_tab[irqindex].mode = 0;
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pin_irq_hdr_tab[irqindex].args = RT_NULL;
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static void gpio_irq_config(uint8_t u8Port, uint16_t u16Pin, uint16_t u16ExInt)
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{
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__IO uint16_t *PCRx;
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uint16_t pin_num;
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pin_num = __CLZ(__RBIT(u16Pin));
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PCRx = (__IO uint16_t *)((uint32_t)(&CM_GPIO->PCRA0) + ((uint32_t)u8Port * 0x40UL) + (pin_num * 4UL));
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MODIFY_REG16(*PCRx, GPIO_PCR_INTE, u16ExInt);
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}
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static rt_err_t hc32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
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{
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struct hc32_pin_irq_map *irq_map;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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stc_extint_init_t stcExtIntInit;
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uint8_t gpio_port;
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uint16_t gpio_pin;
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if ((pin >= PIN_MAX_NUM) || ((PIN_IRQ_ENABLE != enabled) && (PIN_IRQ_DISABLE != enabled)))
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{
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return -RT_ENOSYS;
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}
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irqindex = GPIO_PIN_INDEX(pin);
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if (irqindex >= ITEM_NUM(pin_irq_map))
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{
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return -RT_ENOSYS;
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}
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irq_map = &pin_irq_map[irqindex];
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gpio_port = GPIO_PORT(pin);
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gpio_pin = GPIO_PIN(pin);
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if (enabled == PIN_IRQ_ENABLE)
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{
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == -1)
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{
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rt_hw_interrupt_enable(level);
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return -RT_ENOSYS;
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}
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/* Exint config */
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EXTINT_StructInit(&stcExtIntInit);
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switch (pin_irq_hdr_tab[irqindex].mode)
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{
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case PIN_IRQ_MODE_RISING:
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stcExtIntInit.u32Edge = EXTINT_TRIG_RISING;
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break;
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case PIN_IRQ_MODE_FALLING:
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stcExtIntInit.u32Edge = EXTINT_TRIG_FALLING;
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break;
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case PIN_IRQ_MODE_RISING_FALLING:
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stcExtIntInit.u32Edge = EXTINT_TRIG_BOTH;
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break;
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case PIN_IRQ_MODE_LOW_LEVEL:
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stcExtIntInit.u32Edge = EXTINT_TRIG_LOW;
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break;
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}
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EXTINT_Init(gpio_pin, &stcExtIntInit);
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NVIC_EnableIRQ(irq_map->irq_config.irq_num);
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gpio_irq_config(gpio_port, gpio_pin, PIN_EXTINT_ON);
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}
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else
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{
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level = rt_hw_interrupt_disable();
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gpio_irq_config(gpio_port, gpio_pin, PIN_EXTINT_OFF);
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NVIC_DisableIRQ(irq_map->irq_config.irq_num);
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}
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rt_hw_interrupt_enable(level);
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return RT_EOK;
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}
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static rt_base_t hc32_pin_get(const char *name)
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{
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rt_base_t pin = 0;
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int hw_port_num, hw_pin_num = 0;
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int i, name_len;
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name_len = rt_strlen(name);
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if ((name_len < 4) || (name_len >= 6))
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{
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return -RT_EINVAL;
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}
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if ((name[0] != 'P') || (name[2] != '.'))
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{
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return -RT_EINVAL;
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}
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if ((name[1] >= 'A') && (name[1] <= 'Z'))
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{
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hw_port_num = (int)(name[1] - 'A');
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}
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else
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{
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return -RT_EINVAL;
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}
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for (i = 3; i < name_len; i++)
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{
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hw_pin_num *= 10;
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hw_pin_num += name[i] - '0';
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}
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pin = PIN_NUM(hw_port_num, hw_pin_num);
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|
|
|
return pin;
|
|
}
|
|
|
|
static const struct rt_pin_ops hc32_pin_ops =
|
|
{
|
|
hc32_pin_mode,
|
|
hc32_pin_write,
|
|
hc32_pin_read,
|
|
hc32_pin_attach_irq,
|
|
hc32_pin_detach_irq,
|
|
hc32_pin_irq_enable,
|
|
hc32_pin_get,
|
|
};
|
|
|
|
int rt_hw_pin_init(void)
|
|
{
|
|
uint8_t u32MaxExtInt;
|
|
|
|
/* register extint */
|
|
u32MaxExtInt = ITEM_NUM(pin_irq_map);
|
|
for (uint8_t i = 0; i < u32MaxExtInt; i++)
|
|
{
|
|
hc32_install_irq_handler(&pin_irq_map[i].irq_config, pin_irq_map[i].irq_callback, RT_FALSE);
|
|
}
|
|
|
|
return rt_device_pin_register("pin", &hc32_pin_ops, RT_NULL);
|
|
}
|
|
|
|
#endif
|
|
|
|
#endif /* RT_USING_PIN */
|