411 lines
12 KiB
C
411 lines
12 KiB
C
/******************************************************************************************************************************************
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* 文件名称: system_SWM341.c
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* 功能说明: SWM341单片机的时钟设置
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* 技术支持: http://www.synwit.com.cn/e/tool/gbook/?bid=1
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* 注意事项:
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* 版本日期: V1.1.0 2017年10月25日
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* 升级记录:
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*
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*
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*******************************************************************************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION
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* REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, SYNWIT SHALL NOT BE HELD LIABLE
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* FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
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* OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONN-
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* -ECTION WITH THEIR PRODUCTS.
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*
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* COPYRIGHT 2012 Synwit Technology
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*******************************************************************************************************************************************/
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#include <stdint.h>
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#include "SWM341.h"
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/******************************************************************************************************************************************
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* 系统时钟设定
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*****************************************************************************************************************************************/
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#define SYS_CLK_20MHz 0 //0 内部高频20MHz RC振荡器
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#define SYS_CLK_2M5Hz 1 //1 内部高频2.5MHz RC振荡器
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#define SYS_CLK_40MHz 2 //2 内部高频40MHz RC振荡器
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#define SYS_CLK_5MHz 3 //3 内部高频 5MHz RC振荡器
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#define SYS_CLK_XTAL 4 //4 外部晶体振荡器（4-32MHz）
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#define SYS_CLK_XTAL_DIV8 5 //5 外部晶体振荡器（4-32MHz） 8分频
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#define SYS_CLK_PLL 6 //6 锁相环输出
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#define SYS_CLK_PLL_DIV8 7 //7 锁相环输出 8分频
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#define SYS_CLK_32KHz 8 //8 内部低频32KHz RC 振荡器
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#define SYS_CLK_XTAL_32K 9 //9 外部低频32KHz 晶体振荡器
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#define SYS_CLK SYS_CLK_PLL
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#define __HSI (20000000UL) //高速内部时钟
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#define __LSI ( 32000UL) //低速内部时钟
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#define __HSE (12000000UL) //高速外部时钟
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#define __LSE ( 32768UL) //低速外部时钟
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/********************************** PLL 设定 **********************************************
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* VCO输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV
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* PLL输出频率 = PLL输入时钟 / INDIV * 4 * FBDIV / OUTDIV = VCO输出频率 / OUTDIV
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* 注意：VCO输出频率需要在 [600MHz, 1400MHz] 之间
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*****************************************************************************************/
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#define SYS_PLL_SRC SYS_CLK_XTAL //可取值SYS_CLK_20MHz、SYS_CLK_XTAL
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#define PLL_IN_DIV 3
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#define PLL_FB_DIV 75
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#define PLL_OUT_DIV8 0
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#define PLL_OUT_DIV4 1
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#define PLL_OUT_DIV2 2
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#define PLL_OUT_DIV PLL_OUT_DIV8
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uint32_t SystemCoreClock = __HSI; //System Clock Frequency (Core Clock)
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uint32_t CyclesPerUs = (__HSI / 1000000); //Cycles per micro second
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/******************************************************************************************************************************************
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* 函数名称:
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* 功能说明: This function is used to update the variable SystemCoreClock and must be called whenever the core clock is changed
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* 输 入:
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* 输 出:
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* 注意事项:
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******************************************************************************************************************************************/
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void SystemCoreClockUpdate(void)
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{
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if(SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) //SYS <= HRC
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{
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if(SYS->HRCCR & SYS_HRCCR_DBL_Msk) //HRC = 40MHz
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{
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SystemCoreClock = __HSI*2;
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}
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else //HRC = 20MHz
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{
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SystemCoreClock = __HSI;
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}
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}
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else //SYS <= CLK
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{
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switch((SYS->CLKSEL & SYS_CLKSEL_CLK_Msk) >> SYS_CLKSEL_CLK_Pos)
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{
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case 0:
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SystemCoreClock = __LSI;
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break;
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case 1:
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if(SYS->PLLCR & SYS_PLLCR_INSEL_Msk) //PLL_IN <= HRC
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{
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SystemCoreClock = __HSI;
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}
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else //PLL_IN <= XTAL
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{
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SystemCoreClock = __HSE;
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}
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SystemCoreClock = SystemCoreClock / PLL_IN_DIV * PLL_FB_DIV * 4 / (2 << (2 - PLL_OUT_DIV));
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break;
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case 2:
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SystemCoreClock = __LSE;
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break;
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case 3:
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SystemCoreClock = __HSE;
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break;
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case 4:
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SystemCoreClock = __HSI;
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if(SYS->HRCCR & SYS_HRCCR_DBL_Msk) SystemCoreClock *= 2;
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break;
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}
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if(SYS->CLKSEL & SYS_CLKSEL_CLK_DIVx_Msk) SystemCoreClock /= 8;
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}
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CyclesPerUs = SystemCoreClock / 1000000;
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}
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/******************************************************************************************************************************************
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* 函数名称:
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* 功能说明: The necessary initializaiton of systerm
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* 输 入:
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* 输 出:
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* 注意事项:
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******************************************************************************************************************************************/
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void SystemInit(void)
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{
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SYS->CLKEN0 |= (1 << SYS_CLKEN0_ANAC_Pos);
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Flash_Param_at_xMHz(150);
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switch(SYS_CLK)
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{
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case SYS_CLK_20MHz:
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switchTo20MHz();
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break;
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case SYS_CLK_2M5Hz:
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switchTo2M5Hz();
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break;
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case SYS_CLK_40MHz:
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switchTo40MHz();
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break;
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case SYS_CLK_5MHz:
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switchTo5MHz();
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break;
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case SYS_CLK_XTAL:
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switchToXTAL(0);
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break;
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case SYS_CLK_XTAL_DIV8:
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switchToXTAL(1);
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break;
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case SYS_CLK_PLL:
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switchToPLL(0);
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break;
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case SYS_CLK_PLL_DIV8:
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switchToPLL(1);
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break;
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case SYS_CLK_32KHz:
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switchTo32KHz();
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break;
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case SYS_CLK_XTAL_32K:
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switchToXTAL_32K();
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break;
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}
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SystemCoreClockUpdate();
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if(SystemCoreClock > 120000000)
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{
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Flash_Param_at_xMHz(150);
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}
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else if(SystemCoreClock > 80000000)
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{
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Flash_Param_at_xMHz(120);
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}
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else if(SystemCoreClock > 40000000)
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{
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Flash_Param_at_xMHz(80);
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}
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else if(SystemCoreClock > 30000000)
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{
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Flash_Param_at_xMHz(40);
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}
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else
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{
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Flash_Param_at_xMHz(30);
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}
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PORTM->PULLD &= ~(1 << PIN1);
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PORTM->PULLU &= ~((1 << PIN2) | (1 << PIN3));
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SYS->USBPHYCR &= ~SYS_USBPHYCR_OPMODE_Msk;
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SYS->USBPHYCR |= (1 << SYS_USBPHYCR_OPMODE_Pos); //Non-Driving, DP Pull-Up disable
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}
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void FPU_Enable(void)
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{
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= (0xF << 20);
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#endif
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}
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static void delay_3ms(void)
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{
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uint32_t i;
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if(((SYS->CLKSEL & SYS_CLKSEL_SYS_Msk) == 0) &&
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((((SYS->CLKSEL & SYS_CLKSEL_CLK_Msk) >> SYS_CLKSEL_CLK_Pos) == 0) || //LSI 32KHz
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(((SYS->CLKSEL & SYS_CLKSEL_CLK_Msk) >> SYS_CLKSEL_CLK_Pos) == 2))) //LSE 32KHz
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{
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for(i = 0; i < 20; i++) __NOP();
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}
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else
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{
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for(i = 0; i < 20000; i++) __NOP();
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}
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}
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void switchTo20MHz(void)
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{
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SYS->HRCCR = (1 << SYS_HRCCR_ON_Pos) |
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(0 << SYS_HRCCR_DBL_Pos); //HRC = 20Hz
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delay_3ms();
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SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS <= HRC
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}
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void switchTo2M5Hz(void)
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{
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switchTo20MHz();
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SYS->CLKDIVx_ON = 1;
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SYS->CLKSEL &= ~SYS_CLKSEL_CLK_Msk;
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SYS->CLKSEL |= (4 << SYS_CLKSEL_CLK_Pos); //CLK <= HRC
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SYS->CLKSEL |= (1 << SYS_CLKSEL_CLK_DIVx_Pos);
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delay_3ms();
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SYS->CLKSEL &=~(1 << SYS_CLKSEL_SYS_Pos); //SYS <= HRC/8
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}
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void switchTo40MHz(void)
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{
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SYS->HRCCR = (1 << SYS_HRCCR_ON_Pos) |
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(1 << SYS_HRCCR_DBL_Pos); //HRC = 40MHz
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delay_3ms();
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SYS->CLKSEL |= (1 << SYS_CLKSEL_SYS_Pos); //SYS <= HRC
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}
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void switchTo5MHz(void)
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{
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switchTo40MHz();
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SYS->CLKDIVx_ON = 1;
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SYS->CLKSEL &= ~SYS_CLKSEL_CLK_Msk;
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SYS->CLKSEL |= (4 << SYS_CLKSEL_CLK_Pos); //CLK <= HRC
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SYS->CLKSEL |= (1 << SYS_CLKSEL_CLK_DIVx_Pos);
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delay_3ms();
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SYS->CLKSEL &=~(1 << SYS_CLKSEL_SYS_Pos); //SYS <= HRC/8
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}
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void switchToXTAL(uint32_t div8)
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{
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switchTo20MHz();
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PORT_Init(PORTA, PIN3, PORTA_PIN3_XTAL_IN, 0);
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PORT_Init(PORTA, PIN4, PORTA_PIN4_XTAL_OUT, 0);
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SYS->XTALCR |= (1 << SYS_XTALCR_ON_Pos) | (15 << SYS_XTALCR_DRV_Pos) | (1 << SYS_XTALCR_DET_Pos);
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delay_3ms();
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delay_3ms();
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SYS->CLKDIVx_ON = 1;
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SYS->CLKSEL &= ~SYS_CLKSEL_CLK_Msk;
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SYS->CLKSEL |= (3 << SYS_CLKSEL_CLK_Pos); //CLK <= XTAL
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if(div8) SYS->CLKSEL |= (1 << SYS_CLKSEL_CLK_DIVx_Pos);
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else SYS->CLKSEL &=~(1 << SYS_CLKSEL_CLK_DIVx_Pos);
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SYS->CLKSEL &=~(1 << SYS_CLKSEL_SYS_Pos); //SYS <= XTAL
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}
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void switchToPLL(uint32_t div8)
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{
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switchTo20MHz();
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PLLInit();
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SYS->CLKDIVx_ON = 1;
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SYS->CLKSEL &= ~SYS_CLKSEL_CLK_Msk;
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SYS->CLKSEL |= (1 << SYS_CLKSEL_CLK_Pos); //CLK <= PLL
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if(div8) SYS->CLKSEL |= (1 << SYS_CLKSEL_CLK_DIVx_Pos);
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else SYS->CLKSEL &=~(1 << SYS_CLKSEL_CLK_DIVx_Pos);
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SYS->CLKSEL &=~(1 << SYS_CLKSEL_SYS_Pos); //SYS <= PLL
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}
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void switchTo32KHz(void)
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{
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switchTo20MHz();
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SYS->LRCCR = (1 << SYS_LRCCR_ON_Pos);
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SYS->CLKDIVx_ON = 1;
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SYS->CLKSEL &= ~SYS_CLKSEL_CLK_Msk;
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SYS->CLKSEL |= (0 << SYS_CLKSEL_CLK_Pos); //CLK <= LRC
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SYS->CLKSEL &=~(1 << SYS_CLKSEL_CLK_DIVx_Pos);
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delay_3ms();
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SYS->CLKSEL &=~(1 << SYS_CLKSEL_SYS_Pos); //SYS <= LRC
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}
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void switchToXTAL_32K(void)
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{
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uint32_t i;
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switchTo20MHz();
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SYS->XTALCR |= (1 << SYS_XTALCR_32KON_Pos) | (7 << SYS_XTALCR_32KDRV_Pos) | (1 << SYS_XTALCR_32KDET_Pos);
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for(i = 0; i < 1000; i++) __NOP();
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SYS->CLKDIVx_ON = 1;
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SYS->CLKSEL &= ~SYS_CLKSEL_CLK_Msk;
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SYS->CLKSEL |= (2 << SYS_CLKSEL_CLK_Pos); //CLK <= XTAL_32K
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SYS->CLKSEL &=~(1 << SYS_CLKSEL_CLK_DIVx_Pos);
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delay_3ms();
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SYS->CLKSEL &=~(1 << SYS_CLKSEL_SYS_Pos); //SYS <= XTAL_32K
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}
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void PLLInit(void)
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{
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if(SYS_PLL_SRC == SYS_CLK_20MHz)
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{
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SYS->HRCCR = (1 << SYS_HRCCR_ON_Pos) |
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(0 << SYS_HRCCR_DBL_Pos); //HRC = 20Hz
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delay_3ms();
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SYS->PLLCR |= (1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= HRC
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}
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else if(SYS_PLL_SRC == SYS_CLK_XTAL)
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{
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PORT_Init(PORTA, PIN3, PORTA_PIN3_XTAL_IN, 0);
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PORT_Init(PORTA, PIN4, PORTA_PIN4_XTAL_OUT, 0);
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SYS->XTALCR |= (1 << SYS_XTALCR_ON_Pos) | (15 << SYS_XTALCR_DRV_Pos) | (1 << SYS_XTALCR_DET_Pos);
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delay_3ms();
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delay_3ms();
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SYS->PLLCR &= ~(1 << SYS_PLLCR_INSEL_Pos); //PLL_SRC <= XTAL
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}
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SYS->PLLDIV &= ~(SYS_PLLDIV_INDIV_Msk |
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SYS_PLLDIV_FBDIV_Msk |
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SYS_PLLDIV_OUTDIV_Msk);
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SYS->PLLDIV |= (PLL_IN_DIV << SYS_PLLDIV_INDIV_Pos) |
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(PLL_FB_DIV << SYS_PLLDIV_FBDIV_Pos) |
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(PLL_OUT_DIV<< SYS_PLLDIV_OUTDIV_Pos);
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SYS->PLLCR &= ~(1 << SYS_PLLCR_OFF_Pos);
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while(SYS->PLLLOCK == 0); //等待PLL锁定
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SYS->PLLCR |= (1 << SYS_PLLCR_OUTEN_Pos);
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}
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