56 lines
1.6 KiB
C
56 lines
1.6 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2011-08-08 lgnq first version for LS1B
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* 2015-07-06 chinesebear modified for loongson 1c
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* 2018-01-06 sundm75 modified for smartloong
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*/
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#ifndef __DISPLAY_CONTROLLER_H__
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#define __DISPLAY_CONTROLLER_H__
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#include <rtthread.h>
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#include "ls1c.h"
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#define DC_BASE 0xBC301240 //Display Controller
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/* Frame Buffer registers */
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#define DC_FB_CONFIG __REG32(DC_BASE + 0x000)
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#define DC_FB_BUFFER_ADDR0 __REG32(DC_BASE + 0x020)
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#define DC_FB_BUFFER_STRIDE __REG32(DC_BASE + 0x040)
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#define DC_FB_BUFFER_ORIGIN __REG32(DC_BASE + 0x060)
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#define DC_DITHER_CONFIG __REG32(DC_BASE + 0x120)
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#define DC_DITHER_TABLE_LOW __REG32(DC_BASE + 0x140)
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#define DC_DITHER_TABLE_HIGH __REG32(DC_BASE + 0x160)
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#define DC_PANEL_CONFIG __REG32(DC_BASE + 0x180)
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#define DC_PANEL_TIMING __REG32(DC_BASE + 0x1A0)
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#define DC_HDISPLAY __REG32(DC_BASE + 0x1C0)
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#define DC_HSYNC __REG32(DC_BASE + 0x1E0)
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#define DC_VDISPLAY __REG32(DC_BASE + 0x240)
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#define DC_VSYNC __REG32(DC_BASE + 0x260)
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#define DC_FB_BUFFER_ADDR1 __REG32(DC_BASE + 0x340)
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/* Display Controller driver for 1024x768 16bit */
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#define FB_XSIZE 480
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#define FB_YSIZE 272
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#define CONFIG_VIDEO_16BPP
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#define OSC 24000000 /* Hz */
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#define K1BASE 0xA0000000
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#define KSEG1(addr) ((void *)(K1BASE | (rt_uint32_t)(addr)))
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#define HW_FB_ADDR KSEG1(_rt_framebuffer)
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struct vga_struct
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{
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long pclk;
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int hr,hss,hse,hfl;
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int vr,vss,vse,vfl;
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};
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#endif
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