443 lines
16 KiB
C
443 lines
16 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_DAC_H_
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#define _FSL_DAC_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup dac
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* @{
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*/
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/*! @file */
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief DAC driver version 2.1.0. */
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#define FSL_DAC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
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/*@}*/
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/*!
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* @brief DAC reset control.
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*/
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enum
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{
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kDAC_ResetFIFO = LPDAC_RCR_FIFORST_MASK, /*!< Resets the FIFO pointers and flags. */
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kDAC_ResetLogic = LPDAC_RCR_SWRST_MASK, /*!< Resets all DAC registers and internal logic. */
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};
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/*!
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* @brief DAC interrupts.
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*/
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enum
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{
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kDAC_FIFOFullInterruptEnable = LPDAC_IER_FULL_IE_MASK, /*!< FIFO full interrupt enable. */
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kDAC_FIFOEmptyInterruptEnable = LPDAC_IER_EMPTY_IE_MASK, /*!< FIFO empty interrupt enable. */
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kDAC_FIFOWatermarkInterruptEnable = LPDAC_IER_WM_IE_MASK, /*!< FIFO watermark interrupt enable. */
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kDAC_SwingBackInterruptEnable = LPDAC_IER_SWBK_IE_MASK, /*!< Swing back one cycle complete interrupt enable. */
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kDAC_FIFOOverflowInterruptEnable = LPDAC_IER_OF_IE_MASK, /*!< FIFO overflow interrupt enable. */
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kDAC_FIFOUnderflowInterruptEnable = LPDAC_IER_UF_IE_MASK, /*!< FIFO underflow interrupt enable. */
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#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE
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kDAC_PeriodTriggerCompleteInterruptEnable =
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LPDAC_IER_PTGCOCO_IE_MASK, /*!< Period trigger mode conversion complete interrupt enable */
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#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */
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};
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/*!
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* @brief DAC DMA switchers.
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*/
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enum
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{
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kDAC_FIFOEmptyDMAEnable = LPDAC_DER_EMPTY_DMAEN_MASK, /*!< FIFO empty DMA enable. */
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kDAC_FIFOWatermarkDMAEnable = LPDAC_DER_WM_DMAEN_MASK, /*!< FIFO watermark DMA enable. */
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};
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/*!
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* @brief DAC status flags.
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*/
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enum
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{
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kDAC_FIFOUnderflowFlag = LPDAC_FSR_UF_MASK, /*!< This flag means that there is a new trigger after the buffer is
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empty. The FIFO read pointer will not
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increase in this case and the data sent to DAC analog conversion will not changed. This flag is cleared by writing a 1
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to it. */
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kDAC_FIFOOverflowFlag =
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LPDAC_FSR_OF_MASK, /*!< This flag indicates that data is intended to write into FIFO after the
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buffer is full. The writer pointer will
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not increase in this case. The extra data will not be written into the FIFO. This flag is cleared by writing a 1 to it.
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*/
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kDAC_FIFOSwingBackFlag = LPDAC_FSR_SWBK_MASK, /*!< This flag indicates that the DAC has completed one period of
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conversion in swing back mode. It means
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that the read pointer has increased to the top (write pointer) once and then decreased to zero once. For
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example, after three data is written to FIFO, the writer pointer is now 3. Then, if continually triggered, the
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read pointer will swing like: 0-1-2-1-0-1-2-, and so on. After the fourth trigger, the flag is set. This flag is
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cleared by writing a 1 to it. */
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kDAC_FIFOWatermarkFlag = LPDAC_FSR_WM_MASK, /*!< This field is set if the remaining data in FIFO is less than or
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equal to the setting value of wartermark. By writing data into FIFO by DMA or CPU, this flag is
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cleared automatically when the data in FIFO is more than the setting value of watermark. */
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kDAC_FIFOEmptyFlag = LPDAC_FSR_EMPTY_MASK, /*!< FIFO empty flag. */
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kDAC_FIFOFullFlag = LPDAC_FSR_FULL_MASK, /*!< FIFO full flag. */
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#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE
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kDAC_PeriodTriggerCompleteFlag = LPDAC_FSR_PTGCOCO_MASK, /*!< Period trigger mode conversion complete flag. */
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#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */
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};
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/*!
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* @brief DAC FIFO trigger mode.
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*/
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typedef enum _dac_fifo_trigger_mode
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{
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kDAC_FIFOTriggerByHardwareMode = 0U, /*!< Buffer would be triggered by hardware. */
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kDAC_FIFOTriggerBySoftwareMode = 1U, /*!< Buffer would be triggered by software. */
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} dac_fifo_trigger_mode_t;
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/*!
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* @brief DAC FIFO work mode.
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*/
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typedef enum _dac_fifo_work_mode
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{
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kDAC_FIFODisabled = 0U, /*!< FIFO mode is disabled and buffer mode is enabled. Any data written to DATA[DATA] goes
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to buffer then goes to conversion. */
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kDAC_FIFOWorkAsNormalMode = 1U, /*!< FIFO mode is enabled. Data will be first read from FIFO to buffer then goes to
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conversion. */
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kDAC_FIFOWorkAsSwingMode = 2U, /*!< In swing mode, the read pointer swings between the writer pointer and zero. That
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is, the trigger increases the read pointer till reach the writer pointer and
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decreases the read pointer till zero, and so on. The FIFO empty/full/watermark
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flag will not update during swing back mode. */
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#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE
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kDAC_FIFOWorkAsPeriodTriggerMode =
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3U, /*!< In periodic trigger mode, user only needs to send the first trigger. Then after every [PTG_PERIOD+1]
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RCLK cycles, DAC will be automatically triggered by internal trigger. There will be [PTG_NUM] internal
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triggers, thus in total [PTG_NUM+1] conversions including the first trigger sent by user. User can
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terminate the current conversion queue by clearing the GCR[PTGEN] bit. Then, after the current conversion
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is completed, the conversion is terminated and the PTGCOCO flag is set. If PCR[PTG_NUM] is set to zero,
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there will be infinite triggers following the first hardware/software trigger, until the GCR[PTGEN] is
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cleared by software. In any case, the conversion can be terminated by FIFORST/SWRST. */
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kDAC_FIFOWorkAsPeriodTriggerAndSwingMode = 4U, /*!< Periodically trigger DAC and swing back. */
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#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */
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} dac_fifo_work_mode_t;
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/*!
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* @brief DAC reference voltage source.
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*/
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typedef enum _dac_reference_voltage_source
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{
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#if defined(FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC) && (FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC == 3)
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kDAC_ReferenceVoltageSourceAlt1 = 0U, /*!< The DAC selects VDD_ANA as the reference voltage. */
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kDAC_ReferenceVoltageSourceAlt2 = 1U, /*!< The DAC selects VREF_OUT as the reference voltage. */
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kDAC_ReferenceVoltageSourceAlt3 = 2U, /*!< THe DAC selects VREFH as the reference voltage. */
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#else
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kDAC_ReferenceVoltageSourceAlt1 = 0U, /*!< The DAC selects VREFH_INT as the reference voltage. */
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kDAC_ReferenceVoltageSourceAlt2 = 1U, /*!< The DAC selects VREFH_EXT as the reference voltage. */
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#endif /* FSL_FEATURE_ANALOG_NUM_OF_VREF_SRC */
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} dac_reference_voltage_source_t;
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#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT
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/*
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* @brief DAC internal reference current source
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*/
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typedef enum _dac_reference_current_source
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{
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kDAC_ReferenceCurrentSourcePtat = LPDAC_GCR_IREF_PTAT_EXT_SEL_MASK, /* Internal PTAT Current Reference selected */
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kDAC_ReferenceCurrentSourceZtc = LPDAC_GCR_IREF_ZTC_EXT_SEL_MASK, /* Internal ZTC Current Reference selected */
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} dac_reference_current_source_t;
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#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */
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/*!
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* @brief DAC configuration structure.
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*/
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typedef struct _dac_config
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{
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uint32_t fifoWatermarkLevel; /*!< FIFO's watermark, the max value can be the hardware FIFO size. */
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dac_fifo_trigger_mode_t fifoTriggerMode; /*!< Select the trigger mode for FIFO. */
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dac_fifo_work_mode_t fifoWorkMode; /*!< Select the work mode for FIFO. */
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#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN
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bool enableOpampBuffer; /*!< Opamp is used as buffer. */
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#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_EN */
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#if defined(FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG) && FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG
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bool enableExternalTriggerSource; /* DAC uses another DAC's hardware/software trigger as its trigger source. */
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#endif /* FSL_FEATURE_LPDAC_HAS_GCR_RCV_TRG */
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#if defined(FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL) && FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL
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bool enableLowerLowPowerMode; /*!< Enable the lower low power mode. */
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#else
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bool enableLowPowerMode; /*!< Enable the low power mode. */
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#endif /* FSL_FEATURE_LPDAC_HAS_GCR_BUF_SPD_CTRL */
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#if defined(FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE) && FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE
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uint32_t periodicTriggerNumber; /*!< There will be 'periodicTriggerNumber' internal triggers following the first
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hardware/software trigger. So there will be 'periodicTriggerNumber + 1'
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conversions in total. If set to zero, there will be infinite triggers following
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the first hw/sw trigger, until the GCR[PTGEN] is cleared. */
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uint32_t periodicTriggerWidth; /*!< Control the periodic trigger frequency. There will be 'periodicTriggerWidth + 1'
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RCLK cycles between each periodic trigger. The periodic trigger frequency should
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be configured to not larger than the analog conversion speed. */
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#endif /* FSL_FEATURE_LPDAC_HAS_PERIODIC_TRIGGER_MODE */
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#if defined(FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC) && FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC
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uint32_t syncTime; /*!< RCLK cycles before data latch. accessible range is 0-15. It is used to configure the DAC
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sync cycles which is helpful to reduce glitch on the output. The sync time is (LATCH_CYC+1)
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RCLK cycles. User should configure this register according to the RCLK frequency. The
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recommended sync time is at least 40ns.*/
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#endif /* FSL_FEATURE_LPDAC_HAS_GCR_LATCH_CYC */
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#if defined(FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT) && FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT
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dac_reference_current_source_t referenceCurrentSource; /*!< Select the internal reference current source. */
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#endif /* FSL_FEATURE_LPDAC_HAS_INTERNAL_REFERENCE_CURRENT */
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dac_reference_voltage_source_t referenceVoltageSource; /*!< Select the reference voltage source. */
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} dac_config_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @name Initialization and de-initialization
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* @{
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*/
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/*!
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* @brief Initialize the DAC module with common configuartion.
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*
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* The clock will be enabled in this function.
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*
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* @param base DAC peripheral base address.
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* @param config Pointer to configuration structure.
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*/
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void DAC_Init(LPDAC_Type *base, const dac_config_t *config);
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/*!
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* @brief Get the default settings for initialization's configuration.
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*
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* This function initializes the user configuration structure to a default value. The default values are:
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* @code
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* config->fifoWatermarkLevel = 0U;
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* config->fifoTriggerMode = kDAC_FIFOTriggerByHardwareMode;
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* config->fifoWorkMode = kDAC_FIFODisabled;
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* config->enableLowPowerMode = false;
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* config->referenceVoltageSource = kDAC_ReferenceVoltageSourceAlt1;
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* @endcode
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*
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* @param config Pointer to configuration structure.
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*/
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void DAC_GetDefaultConfig(dac_config_t *config);
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/*!
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* @brief De-initialize the DAC module.
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*
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* The clock will be disabled in this function.
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*
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* @param base DAC peripheral base address.
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*/
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void DAC_Deinit(LPDAC_Type *base);
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/*!
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* @brief Assert the reset control to part hardware.
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*
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* This function is to assert the reset control to part hardware. Responding part hardware would remain reset untill
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* cleared by software.
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*
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* @param base DAC peripheral base address.
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* @param mask The reset control mask, see to _dac_reset_control_t.
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*/
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static inline void DAC_SetReset(LPDAC_Type *base, uint32_t mask)
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{
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base->RCR |= mask;
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}
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/*!
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* @brief Clear the reset control to part hardware.
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*
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* This function is to clear the reset control to part hardware. Responding part hardware would work after the reset
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* control is cleared by software.
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*
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* @param base DAC peripheral base address.
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* @param mask The reset control mask, see to _dac_reset_control_t.
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*/
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static inline void DAC_ClearReset(LPDAC_Type *base, uint32_t mask)
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{
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base->RCR &= ~mask;
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}
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/*!
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* @brief Enable the DAC hardware system or not.
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*
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* This function is to start the Programmable Reference Generator operation or not.
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*
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* @param base DAC peripheral base address.
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* @param enable Assertion of indicated event.
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*/
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static inline void DAC_Enable(LPDAC_Type *base, bool enable)
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{
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if (enable)
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{
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base->GCR |= LPDAC_GCR_DACEN_MASK;
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}
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else
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{
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base->GCR &= ~LPDAC_GCR_DACEN_MASK;
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}
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}
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/* @} */
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/*!
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* @name Interrupts
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* @{
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*/
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/*!
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* @brief Enable the interrupts.
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*
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* @param base DAC peripheral base address.
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* @param mask Mask value of indicated interrupt events. See to _dac_interrupt_enable.
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*/
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static inline void DAC_EnableInterrupts(LPDAC_Type *base, uint32_t mask)
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{
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base->IER |= mask;
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}
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/*!
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* @brief Disable the interrupts.
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*
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* @param base DAC peripheral base address.
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* @param mask Mask value of indicated interrupt events. See to _dac_interrupt_enable.
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*/
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static inline void DAC_DisableInterrupts(LPDAC_Type *base, uint32_t mask)
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{
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base->IER &= ~mask;
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}
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/* @} */
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/*!
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* @name DMA control
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* @{
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*/
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/*!
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* @brief Enable the DMA switchers or not.
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*
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* @param base DAC peripheral base address.
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* @param mask Mask value of indicated DMA requeset. See to _dac_dma_enable.
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* @param enable Enable the DMA or not.
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*/
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static inline void DAC_EnableDMA(LPDAC_Type *base, uint32_t mask, bool enable)
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{
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if (enable)
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{
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base->DER |= mask;
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}
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else
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{
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base->DER &= ~mask;
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}
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}
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/* @} */
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/*!
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* @name Status flags
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* @{
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*/
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/*!
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* @brief Get status flags of DAC module.
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*
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* @param base DAC peripheral base address.
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* @return Mask value of status flags. See to _dac_status_flags.
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*/
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static inline uint32_t DAC_GetStatusFlags(LPDAC_Type *base)
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{
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return base->FSR;
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}
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/*!
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* @brief Clear status flags of DAC module.
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*
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* @param base DAC peripheral base address.
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* @param flags Mask value of status flags to be cleared. See to _dac_status_flags.
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*/
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static inline void DAC_ClearStatusFlags(LPDAC_Type *base, uint32_t flags)
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{
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base->FSR = flags;
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}
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/* @} */
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/*!
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* @name Functional feature
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* @{
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*/
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/*!
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* @brief Set data into the entry of FIFO buffer.
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*
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* @param base DAC peripheral base address.
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* @param value Setting value into FIFO buffer.
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*/
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static inline void DAC_SetData(LPDAC_Type *base, uint32_t value)
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{
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base->DATA = LPDAC_DATA_DATA(value);
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}
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/*!
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* @brief Get the value of the FIFO write pointer.
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*
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* @param base DAC peripheral base address.
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* @return Current value of the FIFO write pointer.
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*/
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static inline uint32_t DAC_GetFIFOWritePointer(LPDAC_Type *base)
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{
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return (LPDAC_FPR_FIFO_WPT_MASK & base->FPR) >> LPDAC_FPR_FIFO_WPT_SHIFT;
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}
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/*!
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* @brief Get the value of the FIFO read pointer.
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*
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* @param base DAC peripheral base address.
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* @return Current value of the FIFO read pointer.
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*/
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static inline uint32_t DAC_GetFIFOReadPointer(LPDAC_Type *base)
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{
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return (LPDAC_FPR_FIFO_RPT_MASK & base->FPR) >> LPDAC_FPR_FIFO_RPT_SHIFT;
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}
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/*!
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* @brief Do software trigger to FIFO when in software mode.
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*
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* @param base DAC peripheral base address.
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*/
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static inline void DAC_DoSoftwareTriggerFIFO(LPDAC_Type *base)
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{
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base->TCR = LPDAC_TCR_SWTRG_MASK;
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}
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/* @} */
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#if defined(__cplusplus)
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}
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#endif
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/*!
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* @}
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*/
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#endif /* _FSL_DAC12_H_ */
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