426 lines
10 KiB
C
426 lines
10 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2012-01-10 bernard porting to AM1808
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <board.h>
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#include "cp15.h"
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#include "mm_page.h"
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#include "mmu.h"
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#include <mm_aspace.h>
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#include <tlb.h>
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#ifdef RT_USING_SMART
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#include <lwp_mm.h>
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#include <lwp_arch.h>
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#include "ioremap.h"
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#else
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#define KERNEL_VADDR_START 0
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#endif
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/* level1 page table, each entry for 1MB memory. */
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volatile unsigned long MMUTable[4 * 1024] __attribute__((aligned(16 * 1024)));
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unsigned long rt_hw_set_domain_register(unsigned long domain_val)
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{
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unsigned long old_domain;
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asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
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asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
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return old_domain;
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}
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void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd,
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rt_uint32_t paddrStart, rt_uint32_t attr)
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{
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volatile rt_uint32_t *pTT;
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volatile int i, nSec;
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pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
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nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
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for(i = 0; i <= nSec; i++)
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{
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*pTT = attr | (((paddrStart >> 20) + i) << 20);
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pTT++;
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}
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}
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void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size)
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{
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/* set page table */
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for(; size > 0; size--)
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{
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if (mdesc->paddr_start == (rt_uint32_t)ARCH_MAP_FAILED)
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mdesc->paddr_start = mdesc->vaddr_start + PV_OFFSET;
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rt_hw_mmu_setmtt(mdesc->vaddr_start, mdesc->vaddr_end,
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mdesc->paddr_start, mdesc->attr);
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mdesc++;
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}
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, (void*)MMUTable, sizeof MMUTable);
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}
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void rt_hw_mmu_init(void)
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{
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rt_cpu_dcache_clean_flush();
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rt_cpu_icache_flush();
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rt_hw_cpu_dcache_disable();
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rt_hw_cpu_icache_disable();
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rt_cpu_mmu_disable();
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/*rt_hw_cpu_dump_page_table(MMUTable);*/
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rt_hw_set_domain_register(0x55555555);
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rt_cpu_tlb_set(MMUTable);
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rt_cpu_mmu_enable();
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rt_hw_cpu_icache_enable();
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rt_hw_cpu_dcache_enable();
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}
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int rt_hw_mmu_map_init(struct rt_aspace *aspace, void* v_address, size_t size, size_t *vtable, size_t pv_off)
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{
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size_t l1_off, va_s, va_e;
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if (!aspace || !vtable)
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{
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return -1;
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}
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va_s = (size_t)v_address;
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va_e = (size_t)v_address + size - 1;
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if ( va_e < va_s)
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{
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return -1;
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}
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va_s >>= ARCH_SECTION_SHIFT;
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va_e >>= ARCH_SECTION_SHIFT;
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if (va_s == 0)
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{
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return -1;
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}
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for (l1_off = va_s; l1_off <= va_e; l1_off++)
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{
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size_t v = vtable[l1_off];
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if (v & ARCH_MMU_USED_MASK)
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{
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return -1;
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}
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}
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#ifdef RT_USING_SMART
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rt_aspace_init(&rt_kernel_space, (void *)USER_VADDR_TOP, 0 - USER_VADDR_TOP, vtable);
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rt_ioremap_start = v_address;
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rt_ioremap_size = size;
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rt_mpr_start = rt_ioremap_start - rt_mpr_size;
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#else
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rt_aspace_init(&rt_kernel_space, (void *)0x1000, 0 - 0x1000, vtable);
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rt_mpr_start = (void *)0 - rt_mpr_size;
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#endif
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return 0;
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}
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int rt_hw_mmu_ioremap_init(rt_aspace_t aspace, void* v_address, size_t size)
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{
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#ifdef RT_IOREMAP_LATE
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size_t loop_va;
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size_t l1_off;
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size_t *mmu_l1, *mmu_l2;
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size_t sections;
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/* for kernel ioremap */
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if ((size_t)v_address < KERNEL_VADDR_START)
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{
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return -1;
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}
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/* must align to section */
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if ((size_t)v_address & ARCH_SECTION_MASK)
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{
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return -1;
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}
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/* must align to section */
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if (size & ARCH_SECTION_MASK)
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{
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return -1;
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}
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loop_va = (size_t)v_address;
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sections = (size >> ARCH_SECTION_SHIFT);
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while (sections--)
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{
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l1_off = (loop_va >> ARCH_SECTION_SHIFT);
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mmu_l1 = (size_t*)aspace->page_table + l1_off;
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RT_ASSERT((*mmu_l1 & ARCH_MMU_USED_MASK) == 0);
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mmu_l2 = (size_t*)rt_pages_alloc(0);
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if (mmu_l2)
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{
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rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2);
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/* cache maintain */
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_l2, ARCH_PAGE_TBL_SIZE);
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*mmu_l1 = (((size_t)mmu_l2 + PV_OFFSET) | 0x1);
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/* cache maintain */
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_l1, 4);
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}
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else
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{
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/* error */
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return -1;
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}
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loop_va += ARCH_SECTION_SIZE;
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}
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#endif
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return 0;
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}
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static void _kenrel_unmap_4K(unsigned long *lv0_tbl, void *v_addr)
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{
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size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK;
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size_t l1_off, l2_off;
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size_t *mmu_l1, *mmu_l2;
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l1_off = (loop_va >> ARCH_SECTION_SHIFT);
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l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT);
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mmu_l1 = (size_t *)lv0_tbl + l1_off;
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if (*mmu_l1 & ARCH_MMU_USED_MASK)
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{
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mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - PV_OFFSET);
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}
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else
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{
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return;
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}
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if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK)
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{
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*(mmu_l2 + l2_off) = 0;
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/* cache maintain */
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_l2 + l2_off, 4);
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if (rt_pages_free(mmu_l2, 0))
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{
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*mmu_l1 = 0;
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_l1, 4);
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}
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}
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loop_va += ARCH_PAGE_SIZE;
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}
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static int _kenrel_map_4K(unsigned long *lv0_tbl, void *v_addr, void *p_addr,
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size_t attr)
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{
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size_t loop_va = (size_t)v_addr & ~ARCH_PAGE_MASK;
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size_t loop_pa = (size_t)p_addr & ~ARCH_PAGE_MASK;
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size_t l1_off, l2_off;
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size_t *mmu_l1, *mmu_l2;
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l1_off = (loop_va >> ARCH_SECTION_SHIFT);
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l2_off = ((loop_va & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT);
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mmu_l1 = (size_t *)lv0_tbl + l1_off;
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if (*mmu_l1 & ARCH_MMU_USED_MASK)
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{
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mmu_l2 = (size_t *)((*mmu_l1 & ~ARCH_PAGE_TBL_MASK) - PV_OFFSET);
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rt_page_ref_inc(mmu_l2, 0);
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}
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else
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{
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mmu_l2 = (size_t *)rt_pages_alloc(0);
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if (mmu_l2)
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{
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rt_memset(mmu_l2, 0, ARCH_PAGE_TBL_SIZE * 2);
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/* cache maintain */
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_l2, ARCH_PAGE_TBL_SIZE);
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*mmu_l1 = (((size_t)mmu_l2 + PV_OFFSET) | 0x1);
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/* cache maintain */
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_l1, 4);
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}
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else
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{
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/* error, quit */
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return -1;
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}
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}
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*(mmu_l2 + l2_off) = (loop_pa | attr);
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/* cache maintain */
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rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, mmu_l2 + l2_off, 4);
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loop_va += ARCH_PAGE_SIZE;
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loop_pa += ARCH_PAGE_SIZE;
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return 0;
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}
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void *rt_hw_mmu_map(rt_aspace_t aspace, void *v_addr, void *p_addr, size_t size,
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size_t attr)
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{
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int ret = -1;
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void *unmap_va = v_addr;
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size_t npages = size >> ARCH_PAGE_SHIFT;
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// TODO trying with HUGEPAGE here
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while (npages--)
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{
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ret = _kenrel_map_4K(aspace->page_table, v_addr, p_addr, attr);
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if (ret != 0)
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{
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/* error, undo map */
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while (unmap_va != v_addr)
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{
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rt_enter_critical();
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_kenrel_unmap_4K(aspace->page_table, (void *)unmap_va);
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rt_exit_critical();
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unmap_va += ARCH_PAGE_SIZE;
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}
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break;
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}
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v_addr += ARCH_PAGE_SIZE;
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p_addr += ARCH_PAGE_SIZE;
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}
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if (ret == 0)
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{
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return v_addr;
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}
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return NULL;
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}
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void rt_hw_mmu_unmap(rt_aspace_t aspace, void *v_addr, size_t size)
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{
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// caller guarantee that v_addr & size are page aligned
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size_t npages = size >> ARCH_PAGE_SHIFT;
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if (!aspace->page_table)
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{
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return;
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}
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while (npages--)
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{
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rt_enter_critical();
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_kenrel_unmap_4K(aspace->page_table, v_addr);
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rt_exit_critical();
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v_addr += ARCH_PAGE_SIZE;
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}
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}
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void rt_hw_aspace_switch(rt_aspace_t aspace)
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{
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if (aspace != &rt_kernel_space)
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{
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void *pgtbl = aspace->page_table;
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pgtbl = rt_kmem_v2p(pgtbl);
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rt_hw_mmu_switch(pgtbl);
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rt_hw_tlb_invalidate_all_local();
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}
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}
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void init_mm_setup(unsigned int *mtbl, unsigned int size, unsigned int pv_off)
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{
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unsigned int va;
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for (va = 0; va < 0x1000; va++)
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{
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unsigned int vaddr = (va << 20);
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if (vaddr >= KERNEL_VADDR_START && vaddr - KERNEL_VADDR_START < size)
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{
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mtbl[va] = ((va << 20) + pv_off) | NORMAL_MEM;
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}
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else if (vaddr >= (KERNEL_VADDR_START + pv_off) && vaddr - (KERNEL_VADDR_START + pv_off) < size)
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{
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mtbl[va] = (va << 20) | NORMAL_MEM;
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}
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else
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{
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mtbl[va] = 0;
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}
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}
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}
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void *rt_hw_mmu_v2p(rt_aspace_t aspace, void* v_addr)
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{
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size_t l1_off, l2_off;
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size_t *mmu_l1, *mmu_l2;
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size_t tmp;
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size_t pa;
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l1_off = (size_t)v_addr >> ARCH_SECTION_SHIFT;
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RT_ASSERT(aspace);
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mmu_l1 = (size_t*)aspace->page_table + l1_off;
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tmp = *mmu_l1;
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switch (tmp & ARCH_MMU_USED_MASK)
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{
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case 0: /* not used */
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break;
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case 1: /* page table */
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mmu_l2 = (size_t *)((tmp & ~ARCH_PAGE_TBL_MASK) - PV_OFFSET);
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l2_off = (((size_t)v_addr & ARCH_SECTION_MASK) >> ARCH_PAGE_SHIFT);
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pa = *(mmu_l2 + l2_off);
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if (pa & ARCH_MMU_USED_MASK)
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{
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if ((pa & ARCH_MMU_USED_MASK) == 1)
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{
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/* large page, not support */
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break;
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}
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pa &= ~(ARCH_PAGE_MASK);
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pa += ((size_t)v_addr & ARCH_PAGE_MASK);
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return (void*)pa;
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}
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break;
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case 2:
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case 3:
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/* section */
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if (tmp & ARCH_TYPE_SUPERSECTION)
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{
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/* super section, not support */
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break;
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}
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pa = (tmp & ~ARCH_SECTION_MASK);
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pa += ((size_t)v_addr & ARCH_SECTION_MASK);
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return (void*)pa;
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}
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return ARCH_MAP_FAILED;
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}
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int rt_hw_mmu_control(struct rt_aspace *aspace, void *vaddr, size_t size,
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enum rt_mmu_cntl cmd)
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{
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return -RT_ENOSYS;
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}
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