643 lines
20 KiB
C
643 lines
20 KiB
C
/*
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* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-04-28 CDT first version
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*/
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "drv_eth.h"
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#if defined(BSP_USING_ETH)
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#include <netif/ethernetif.h>
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#include <lwipopts.h>
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#include "drv_irq.h"
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#include "board_config.h"
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/*******************************************************************************
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* Local pre-processor symbols/macros ('#define')
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******************************************************************************/
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//#define DRV_DEBUG
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#define LOG_TAG "drv.eth"
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#include <drv_log.h>
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#define MAX_ADDR_LEN 6
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/*******************************************************************************
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* Local type definitions ('typedef')
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******************************************************************************/
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struct hc32_eth
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{
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/* inherit from ethernet device */
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struct eth_device parent;
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#if !(defined(PHY_USING_INTERRUPT_MODE) && defined(ETH_USING_INTERFACE_RMII))
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rt_timer_t poll_link_timer;
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#endif
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/* interface address info, hw address */
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rt_uint8_t dev_addr[MAX_ADDR_LEN];
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/* ETH_Speed */
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rt_uint32_t eth_speed;
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/* ETH_Duplex_Mode */
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rt_uint32_t eth_mode;
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/* eth irq */
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struct hc32_irq_config irq_config;
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func_ptr_t irq_callback;
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};
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/* eth phy status */
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enum
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{
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ETH_PHY_LINK = 0x01U,
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ETH_PHY_100M = 0x02U,
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ETH_PHY_FULL_DUPLEX = 0x04U,
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};
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/*******************************************************************************
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* Global variable definitions (declared in header file with 'extern')
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******************************************************************************/
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extern rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx);
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extern rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx);
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/*******************************************************************************
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* Local function prototypes ('static')
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******************************************************************************/
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static void eth_global_irq_handle(void);
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/*******************************************************************************
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* Local variable definitions ('static')
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******************************************************************************/
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static stc_eth_handle_t EthHandle;
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/* Ethernet Tx,Rx DMA Descriptor */
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static stc_eth_dma_desc_t *EthDmaTxDscrTab, *EthDmaRxDscrTab;
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/* Ethernet Transmit,Receive Buffer */
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static rt_uint8_t *EthTxBuff, *EthRxBuff;
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static struct hc32_eth hc32_eth_device =
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{
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.irq_config = ETH_IRQ_CONFIG,
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.irq_callback = eth_global_irq_handle,
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};
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/*******************************************************************************
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* Function implementation - global ('extern') and local ('static')
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******************************************************************************/
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static rt_err_t rt_hc32_eth_init(rt_device_t dev)
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{
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stc_eth_init_t stcEthInit;
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uint16_t u16RegVal;
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/* Enable ETH clock */
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FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_ETHMAC, ENABLE);
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/* Init Ethernet GPIO */
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rt_hw_eth_phy_reset(CM_ETH);
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rt_hw_eth_board_init(CM_ETH);
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/* Reset ETHERNET */
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(void)ETH_DeInit();
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/* Configure structure initialization */
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(void)ETH_CommStructInit(&EthHandle.stcCommInit);
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(void)ETH_StructInit(&stcEthInit);
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EthHandle.stcCommInit.u16AutoNego = ETH_AUTO_NEGO_DISABLE;
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EthHandle.stcCommInit.au8MacAddr[0] = hc32_eth_device.dev_addr[0];
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EthHandle.stcCommInit.au8MacAddr[1] = hc32_eth_device.dev_addr[1];
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EthHandle.stcCommInit.au8MacAddr[2] = hc32_eth_device.dev_addr[2];
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EthHandle.stcCommInit.au8MacAddr[3] = hc32_eth_device.dev_addr[3];
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EthHandle.stcCommInit.au8MacAddr[4] = hc32_eth_device.dev_addr[4];
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EthHandle.stcCommInit.au8MacAddr[5] = hc32_eth_device.dev_addr[5];
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#ifdef ETH_USING_INTERFACE_RMII
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EthHandle.stcCommInit.u32Interface = ETH_MAC_IF_RMII;
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#else
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EthHandle.stcCommInit.u32Interface = ETH_MAC_IF_MII;
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#endif
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EthHandle.stcCommInit.u32ReceiveMode = ETH_RX_MD_INT;
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#ifdef RT_LWIP_USING_HW_CHECKSUM
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EthHandle.stcCommInit.u32ChecksumMode = ETH_MAC_CHECKSUM_MD_HW;
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#else
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EthHandle.stcCommInit.u32ChecksumMode = ETH_MAC_CHECKSUM_MD_SW;
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#endif
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/* Configure ethernet peripheral */
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if (LL_OK != ETH_Init(&EthHandle, &stcEthInit))
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{
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LOG_E("eth hardware init failed");
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}
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else
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{
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LOG_D("eth hardware init success");
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}
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/* Initialize Tx Descriptors list: Chain Mode */
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(void)ETH_DMA_TxDescListInit(&EthHandle, EthDmaTxDscrTab, EthTxBuff, ETH_TX_BUF_NUM);
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/* Initialize Rx Descriptors list: Chain Mode */
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(void)ETH_DMA_RxDescListInit(&EthHandle, EthDmaRxDscrTab, EthRxBuff, ETH_RX_BUF_NUM);
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/* Enable ETH interrupt */
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NVIC_EnableIRQ(hc32_eth_device.irq_config.irq_num);
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/* Enable MAC and DMA transmission and reception */
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if (LL_OK == ETH_Start())
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{
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LOG_D("eth hardware start");
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}
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else
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{
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LOG_E("eth hardware start faild");
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return -RT_ERROR;
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}
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/* Configure PHY LED mode */
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u16RegVal = PHY_PAGE_ADDR_7;
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(void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal);
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(void)ETH_PHY_ReadReg(&EthHandle, PHY_P7_IWLFR, &u16RegVal);
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MODIFY_REG16(u16RegVal, PHY_LED_SELECT, PHY_LED_SELECT_10);
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(void)ETH_PHY_WriteReg(&EthHandle, PHY_P7_IWLFR, u16RegVal);
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u16RegVal = PHY_PAGE_ADDR_0;
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(void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal);
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#ifdef ETH_USING_INTERFACE_RMII
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/* Disable Power Saving Mode */
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(void)ETH_PHY_ReadReg(&EthHandle, PHY_PSMR, &u16RegVal);
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CLR_REG16_BIT(u16RegVal, PHY_EN_PWR_SAVE);
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(void)ETH_PHY_WriteReg(&EthHandle, PHY_PSMR, u16RegVal);
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#endif
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return RT_EOK;
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}
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static rt_err_t rt_hc32_eth_open(rt_device_t dev, rt_uint16_t oflag)
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{
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LOG_D("eth open");
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return RT_EOK;
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}
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static rt_err_t rt_hc32_eth_close(rt_device_t dev)
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{
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LOG_D("eth close");
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return RT_EOK;
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}
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static rt_size_t rt_hc32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
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{
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LOG_D("eth read");
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_size_t rt_hc32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
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{
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LOG_D("eth write");
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rt_set_errno(-RT_ENOSYS);
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return 0;
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}
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static rt_err_t rt_hc32_eth_control(rt_device_t dev, int cmd, void *args)
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{
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switch (cmd)
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{
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case NIOCTL_GADDR:
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/* get mac address */
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if (args)
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{
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SMEMCPY(args, hc32_eth_device.dev_addr, 6);
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}
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else
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{
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return -RT_ERROR;
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}
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break;
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default :
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break;
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}
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return RT_EOK;
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}
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/* ethernet device interface */
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/* transmit data*/
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rt_err_t rt_hc32_eth_tx(rt_device_t dev, struct pbuf *p)
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{
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rt_err_t errval = RT_ERROR;
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struct pbuf *q;
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uint8_t *txBuffer;
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__IO stc_eth_dma_desc_t *DmaTxDesc;
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uint32_t byteCnt;
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uint32_t frameLength = 0UL;
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uint32_t bufferOffset;
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uint32_t payloadOffset;
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DmaTxDesc = EthHandle.stcTxDesc;
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txBuffer = (uint8_t *)((EthHandle.stcTxDesc)->u32Buf1Addr);
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bufferOffset = 0UL;
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/* Copy frame from pbufs to driver buffers */
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for (q = p; q != NULL; q = q->next)
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{
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/* If this buffer isn't available, goto error */
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if (0UL != (DmaTxDesc->u32ControlStatus & ETH_DMA_TXDESC_OWN))
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{
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LOG_D("buffer not valid");
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errval = (err_t)ERR_USE;
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goto error;
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}
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/* Get bytes in current lwIP buffer */
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byteCnt = q->len;
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payloadOffset = 0UL;
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/* Check if the length of data to copy is bigger than Tx buffer size */
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while ((byteCnt + bufferOffset) > ETH_TX_BUF_SIZE)
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{
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/* Copy data to Tx buffer*/
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SMEMCPY((uint8_t *) & (txBuffer[bufferOffset]), (uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), (ETH_TX_BUF_SIZE - bufferOffset));
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/* Point to next descriptor */
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DmaTxDesc = (stc_eth_dma_desc_t *)(DmaTxDesc->u32Buf2NextDescAddr);
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/* Check if the buffer is available */
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if (0UL != (DmaTxDesc->u32ControlStatus & ETH_DMA_TXDESC_OWN))
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{
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errval = (err_t)ERR_USE;
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goto error;
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}
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txBuffer = (uint8_t *)(DmaTxDesc->u32Buf1Addr);
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byteCnt = byteCnt - (ETH_TX_BUF_SIZE - bufferOffset);
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payloadOffset = payloadOffset + (ETH_TX_BUF_SIZE - bufferOffset);
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frameLength = frameLength + (ETH_TX_BUF_SIZE - bufferOffset);
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bufferOffset = 0UL;
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}
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/* Copy the remaining bytes */
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SMEMCPY((uint8_t *) & (txBuffer[bufferOffset]), (uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), byteCnt);
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bufferOffset = bufferOffset + byteCnt;
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frameLength = frameLength + byteCnt;
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}
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LOG_D("transmit frame length :%d", framelength);
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/* Prepare transmit descriptors to give to DMA */
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(void)ETH_DMA_SetTransFrame(&EthHandle, frameLength);
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errval = (err_t)ERR_OK;
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error:
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/* When Transmit Underflow flag is set, clear it and issue a Transmit Poll Demand to resume transmission */
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if (RESET != ETH_DMA_GetStatus(ETH_DMA_FLAG_UNS))
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{
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/* Clear DMA UNS flag */
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ETH_DMA_ClearStatus(ETH_DMA_FLAG_UNS);
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/* Resume DMA transmission */
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WRITE_REG32(CM_ETH->DMA_TXPOLLR, 0UL);
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}
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return errval;
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}
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/* receive data*/
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struct pbuf *rt_hc32_eth_rx(rt_device_t dev)
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{
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struct pbuf *p = NULL;
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struct pbuf *q;
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uint32_t len;
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uint8_t *rxBuffer;
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__IO stc_eth_dma_desc_t *DmaRxDesc;
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uint32_t byteCnt;
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uint32_t bufferOffset;
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uint32_t payloadOffset;
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uint32_t i;
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/* Get received frame */
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if (LL_OK != ETH_DMA_GetReceiveFrame_Int(&EthHandle))
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{
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LOG_D("receive frame faild");
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return NULL;
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}
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/* Obtain the size of the packet */
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len = (EthHandle.stcRxFrame).u32Len;
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rxBuffer = (uint8_t *)(EthHandle.stcRxFrame).u32Buf;
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LOG_D("receive frame len : %d", len);
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if (len > 0UL)
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{
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/* Allocate a pbuf chain of pbufs from the Lwip buffer pool */
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p = pbuf_alloc(PBUF_RAW, (uint16_t)len, PBUF_POOL);
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}
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if (p != NULL)
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{
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DmaRxDesc = (EthHandle.stcRxFrame).pstcFSDesc;
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bufferOffset = 0UL;
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for (q = p; q != NULL; q = q->next)
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{
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byteCnt = q->len;
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payloadOffset = 0UL;
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/* Check if the length of bytes to copy in current pbuf is bigger than Rx buffer size */
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while ((byteCnt + bufferOffset) > ETH_RX_BUF_SIZE)
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{
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/* Copy data to pbuf */
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SMEMCPY((uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), (uint8_t *) & (rxBuffer[bufferOffset]), (ETH_RX_BUF_SIZE - bufferOffset));
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/* Point to next descriptor */
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DmaRxDesc = (stc_eth_dma_desc_t *)(DmaRxDesc->u32Buf2NextDescAddr);
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rxBuffer = (uint8_t *)(DmaRxDesc->u32Buf1Addr);
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byteCnt = byteCnt - (ETH_RX_BUF_SIZE - bufferOffset);
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payloadOffset = payloadOffset + (ETH_RX_BUF_SIZE - bufferOffset);
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bufferOffset = 0UL;
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}
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/* Copy remaining data in pbuf */
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SMEMCPY((uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), (uint8_t *) & (rxBuffer[bufferOffset]), byteCnt);
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bufferOffset = bufferOffset + byteCnt;
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}
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}
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/* Release descriptors to DMA */
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DmaRxDesc = (EthHandle.stcRxFrame).pstcFSDesc;
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for (i = 0UL; i < (EthHandle.stcRxFrame).u32SegCount; i++)
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{
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DmaRxDesc->u32ControlStatus |= ETH_DMA_RXDESC_OWN;
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DmaRxDesc = (stc_eth_dma_desc_t *)(DmaRxDesc->u32Buf2NextDescAddr);
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}
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/* Clear Segment_Count */
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(EthHandle.stcRxFrame).u32SegCount = 0UL;
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/* When Rx Buffer unavailable flag is set, clear it and resume reception */
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if (RESET != ETH_DMA_GetStatus(ETH_DMA_FLAG_RUS))
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{
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/* Clear DMA RUS flag */
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ETH_DMA_ClearStatus(ETH_DMA_FLAG_RUS);
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/* Resume DMA reception */
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WRITE_REG32(CM_ETH->DMA_RXPOLLR, 0UL);
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}
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return p;
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}
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static void hc32_eth_irq_handle(stc_eth_handle_t *eth_handle)
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{
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rt_err_t result;
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(void)eth_handle;
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/* Frame received */
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if (RESET != ETH_DMA_GetStatus(ETH_DMA_FLAG_RIS))
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{
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result = eth_device_ready(&(hc32_eth_device.parent));
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if (result != RT_EOK)
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{
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LOG_I("eth rx complete callback err = %d", result);
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}
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/* Clear the Eth DMA Rx IT pending bits */
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ETH_DMA_ClearStatus(ETH_DMA_FLAG_RIS | ETH_DMA_FLAG_NIS);
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}
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}
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/* interrupt service routine */
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static void eth_global_irq_handle(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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hc32_eth_irq_handle(&EthHandle);
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/* leave interrupt */
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rt_interrupt_leave();
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}
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static void hc32_phy_link_change(void)
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{
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static rt_uint8_t phy_status = 0;
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rt_uint8_t phy_status_new = 0;
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uint16_t u16RegVal = 0U;
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uint16_t u16Page = 0U;
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/* Switch page */
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(void)ETH_PHY_ReadReg(&EthHandle, PHY_PSR, &u16Page);
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if (u16Page != PHY_PAGE_ADDR_0)
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{
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u16RegVal = PHY_PAGE_ADDR_0;
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(void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal);
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}
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/* Read PHY_BSR */
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(void)ETH_PHY_ReadReg(&EthHandle, PHY_BASIC_STATUS_REG, &u16RegVal);
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LOG_D("phy basic status reg is 0x%X", u16RegVal);
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if ((0x0000U != u16RegVal) && (0xFFFFU != u16RegVal))
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{
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if (u16RegVal & (PHY_AUTONEGO_COMPLETE_MASK | PHY_LINKED_STATUS_MASK))
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{
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phy_status_new |= ETH_PHY_LINK;
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if (0U != (u16RegVal & (PHY_100BASE_TX_FD | PHY_10BASE_T_FD)))
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{
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phy_status_new |= ETH_PHY_FULL_DUPLEX;
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}
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if (0U != (u16RegVal & (PHY_100BASE_TX_FD | PHY_100BASE_TX_HD)))
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{
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phy_status_new |= ETH_PHY_100M;
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}
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}
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}
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/* Restore page */
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if (u16Page != PHY_PAGE_ADDR_0)
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{
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(void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16Page);
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}
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if (phy_status != phy_status_new)
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{
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phy_status = phy_status_new;
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if (phy_status & ETH_PHY_LINK)
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{
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if (phy_status & ETH_PHY_FULL_DUPLEX)
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{
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hc32_eth_device.eth_mode = ETH_MAC_DUPLEX_MD_FULL;
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}
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else
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{
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hc32_eth_device.eth_mode = ETH_MAC_DUPLEX_MD_HALF;
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}
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if (phy_status & ETH_PHY_100M)
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{
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hc32_eth_device.eth_speed = ETH_MAC_SPEED_100M;
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}
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else
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{
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hc32_eth_device.eth_speed = ETH_MAC_SPEED_10M;
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}
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LOG_D("link up");
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eth_device_linkchange(&hc32_eth_device.parent, RT_TRUE);
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}
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else
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{
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LOG_I("link down");
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eth_device_linkchange(&hc32_eth_device.parent, RT_FALSE);
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}
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}
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}
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#if defined(PHY_USING_INTERRUPT_MODE) && defined(ETH_USING_INTERFACE_RMII)
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static void eth_phy_irq_handler(void *args)
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{
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rt_uint16_t status = 0;
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ETH_PHY_ReadReg(&EthHandle, PHY_IISDR, &status);
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LOG_D("phy interrupt status reg is 0x%X", status);
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hc32_phy_link_change();
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}
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#endif
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static void hc32_phy_monitor_thread(void *parameter)
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{
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uint8_t phy_addr = 0xFF;
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uint8_t detected_count = 0;
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/* phy search */
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while (phy_addr == 0xFF)
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{
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rt_uint16_t i, temp;
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for (i = 0; i <= 0x1F; i++)
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{
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EthHandle.stcCommInit.u16PhyAddr = i;
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ETH_PHY_ReadReg(&EthHandle, PHY_ID1_REG, &temp);
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if (temp != 0xFFFF && temp != 0x00)
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{
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phy_addr = i;
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break;
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}
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}
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detected_count++;
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rt_thread_mdelay(1000);
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if (detected_count > 10)
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{
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LOG_E("No PHY device was detected!");
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}
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}
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LOG_D("Found a phy, address:0x%02X", phy_addr);
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/* Reset PHY */
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ETH_PHY_WriteReg(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_RESET_MASK);
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rt_thread_mdelay(2000);
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ETH_PHY_WriteReg(&EthHandle, PHY_BASIC_CONTROL_REG, PHY_AUTO_NEGOTIATION_MASK);
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hc32_phy_link_change();
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#if defined(PHY_USING_INTERRUPT_MODE) && defined(ETH_USING_INTERFACE_RMII)
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/* configuration intterrupt pin */
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rt_pin_mode(ETH_PHY_INT_PIN, PIN_MODE_INPUT_PULLUP);
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rt_pin_attach_irq(ETH_PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_irq_handler, (void *)"callbackargs");
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rt_pin_irq_enable(ETH_PHY_INT_PIN, PIN_IRQ_ENABLE);
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uint16_t u16RegVal;
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/* Configure PHY to generate an interrupt when Eth Link state changes */
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u16RegVal = PHY_PAGE_ADDR_7;
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(void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal);
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/* Enable Interrupt on change of link status */
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(void)ETH_PHY_ReadReg(&EthHandle, PHY_P7_IWLFR, &u16RegVal);
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SET_REG16_BIT(u16RegVal, PHY_INT_LINK_CHANGE);
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(void)ETH_PHY_WriteReg(&EthHandle, PHY_P7_IWLFR, u16RegVal);
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u16RegVal = PHY_PAGE_ADDR_0;
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(void)ETH_PHY_WriteReg(&EthHandle, PHY_PSR, u16RegVal);
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#else
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hc32_eth_device.poll_link_timer = rt_timer_create("eth_phy_link", (void (*)(void *))hc32_phy_link_change,
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NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
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if (!hc32_eth_device.poll_link_timer || rt_timer_start(hc32_eth_device.poll_link_timer) != RT_EOK)
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{
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LOG_E("Start eth phy link change detection timer failed");
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}
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#endif
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}
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/* Register the eth device */
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static int rt_hw_hc32_eth_init(void)
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{
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rt_err_t state = RT_EOK;
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/* register eth handler */
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hc32_install_irq_handler(&hc32_eth_device.irq_config, hc32_eth_device.irq_callback, RT_FALSE);
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/* Prepare receive and send buffers */
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EthRxBuff = (rt_uint8_t *)rt_calloc(ETH_RX_BUF_NUM, ETH_MAX_PACKET_SIZE);
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if (EthRxBuff == RT_NULL)
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{
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LOG_E("No memory");
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state = -RT_ENOMEM;
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goto __exit;
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}
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EthTxBuff = (rt_uint8_t *)rt_calloc(ETH_TX_BUF_NUM, ETH_MAX_PACKET_SIZE);
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if (EthTxBuff == RT_NULL)
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{
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LOG_E("No memory");
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state = -RT_ENOMEM;
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goto __exit;
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}
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EthDmaRxDscrTab = (stc_eth_dma_desc_t *)rt_calloc(ETH_RX_BUF_NUM, sizeof(stc_eth_dma_desc_t));
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if (EthDmaRxDscrTab == RT_NULL)
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{
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LOG_E("No memory");
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state = -RT_ENOMEM;
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goto __exit;
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}
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EthDmaTxDscrTab = (stc_eth_dma_desc_t *)rt_calloc(ETH_TX_BUF_NUM, sizeof(stc_eth_dma_desc_t));
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if (EthDmaTxDscrTab == RT_NULL)
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{
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LOG_E("No memory");
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state = -RT_ENOMEM;
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goto __exit;
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}
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hc32_eth_device.eth_speed = ETH_MAC_SPEED_100M;
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hc32_eth_device.eth_mode = ETH_MAC_DUPLEX_MD_FULL;
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/* 00-80 uid */
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hc32_eth_device.dev_addr[0] = 0x02;
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hc32_eth_device.dev_addr[1] = 0x80;
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hc32_eth_device.dev_addr[2] = 0x00;
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/* generate MAC addr from unique ID */
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hc32_eth_device.dev_addr[3] = (rt_uint8_t)READ_REG32(CM_EFM->UQID0);
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hc32_eth_device.dev_addr[4] = (rt_uint8_t)READ_REG32(CM_EFM->UQID1);
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hc32_eth_device.dev_addr[5] = (rt_uint8_t)READ_REG32(CM_EFM->UQID2);
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hc32_eth_device.parent.parent.init = rt_hc32_eth_init;
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hc32_eth_device.parent.parent.open = rt_hc32_eth_open;
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hc32_eth_device.parent.parent.close = rt_hc32_eth_close;
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hc32_eth_device.parent.parent.read = rt_hc32_eth_read;
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hc32_eth_device.parent.parent.write = rt_hc32_eth_write;
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hc32_eth_device.parent.parent.control = rt_hc32_eth_control;
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hc32_eth_device.parent.parent.user_data = RT_NULL;
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hc32_eth_device.parent.eth_rx = rt_hc32_eth_rx;
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hc32_eth_device.parent.eth_tx = rt_hc32_eth_tx;
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/* register eth device */
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state = eth_device_init(&(hc32_eth_device.parent), "e0");
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if (RT_EOK == state)
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{
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LOG_D("eth device init success");
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}
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else
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{
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LOG_E("eth device init faild: %d", state);
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state = -RT_ERROR;
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goto __exit;
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}
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/* start phy monitor */
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rt_thread_t tid;
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tid = rt_thread_create("phy_monitor", hc32_phy_monitor_thread, RT_NULL, 1024, 12, 5);
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if (tid != RT_NULL)
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{
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rt_thread_startup(tid);
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}
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else
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{
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state = -RT_ERROR;
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}
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__exit:
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if (state != RT_EOK)
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{
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if (EthRxBuff)
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{
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rt_free(EthRxBuff);
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}
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if (EthTxBuff)
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{
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rt_free(EthTxBuff);
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}
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if (EthDmaRxDscrTab)
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{
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rt_free(EthDmaRxDscrTab);
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}
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if (EthDmaTxDscrTab)
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{
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rt_free(EthDmaTxDscrTab);
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}
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}
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return state;
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}
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INIT_DEVICE_EXPORT(rt_hw_hc32_eth_init);
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#endif
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