368 lines
13 KiB
C
368 lines
13 KiB
C
/***************************************************************************//**
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* @file
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* @brief Flash controller module (MSC) peripheral API for EFM32
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* @author Energy Micro AS
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* @version 2.3.2
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*******************************************************************************
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* @section License
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* <b>(C) Copyright 2010 Energy Micro AS, http://www.energymicro.com</b>
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*******************************************************************************
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*
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* This source code is the property of Energy Micro AS. The source and compiled
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* code may only be used on Energy Micro "EFM32" microcontrollers.
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*
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* This copyright notice may not be removed from the source code nor changed.
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*
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* DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Energy Micro AS has no
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* obligation to support this Software. Energy Micro AS is providing the
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* Software "AS IS", with no express or implied warranties of any kind,
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* including, but not limited to, any implied warranties of merchantability
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* or fitness for any particular purpose or warranties against infringement
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* of any proprietary rights of a third party.
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*
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* Energy Micro AS will not be liable for any consequential, incidental, or
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* special damages, or any other relief, or for any claim by any third party,
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* arising from your use of this Software.
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*
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******************************************************************************/
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#ifndef __EFM32_MSC_H
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#define __EFM32_MSC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#include "efm32.h"
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#include "efm32_bitband.h"
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/***************************************************************************//**
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* @addtogroup EFM32_Library
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* @{
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******************************************************************************/
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/***************************************************************************//**
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* @addtogroup MSC
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* @brief Flash controller (MSC) peripheral API for EFM32
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* @{
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******************************************************************************/
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/*******************************************************************************
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************************* DEFINES *****************************************
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******************************************************************************/
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/**
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* @brief
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* The timeout used while waiting for the flash to become ready after
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* a write. This number indicates the number of iterations to perform before
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* issuing a timeout.
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* @note
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* This timeout is set very large (in the order of 100x longer than
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* necessary). This is to avoid any corner cases.
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*
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*/
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#define MSC_PROGRAM_TIMEOUT 10000000ul
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/*******************************************************************************
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************************* TYPEDEFS ****************************************
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******************************************************************************/
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/** Return codes for writing/erasing the flash */
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typedef enum
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{
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mscReturnOk = 0, /**< Flash write/erase successful. */
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mscReturnInvalidAddr = -1, /**< Invalid address. Write to an address that is not flash. */
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mscReturnLocked = -2, /**< Flash address is locked. */
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mscReturnTimeOut = -3, /**< Timeout while writing to flash. */
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mscReturnUnaligned = -4 /**< Unaligned access to flash. */
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} msc_Return_TypeDef;
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#if defined (_EFM32_GIANT_FAMILY)
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/** Strategy for prioritized bus access */
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typedef enum {
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mscBusStrategyCPU = MSC_READCTRL_BUSSTRATEGY_CPU, /**< Prioritize CPU bus accesses */
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mscBusStrategyDMA = MSC_READCTRL_BUSSTRATEGY_DMA, /**< Prioritize DMA bus accesses */
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mscBusStrategyDMAEM2 = MSC_READCTRL_BUSSTRATEGY_DMAEM2, /**< Prioritize DMAEM2 for bus accesses */
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mscBusStrategyNone = MSC_READCTRL_BUSSTRATEGY_NONE /**< No unit has bus priority */
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} mscBusStrategy_Typedef;
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#endif
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/*******************************************************************************
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************************* PROTOTYPES **************************************
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******************************************************************************/
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void MSC_Deinit(void);
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void MSC_Init(void);
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/***************************************************************************//**
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* @brief
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* Clear one or more pending MSC interrupts.
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*
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* @param[in] flags
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* Pending MSC intterupt source to clear. Use a bitwise logic OR combination
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* of valid interrupt flags for the MSC module (MSC_IF_nnn).
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******************************************************************************/
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static __INLINE void MSC_IntClear(uint32_t flags)
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{
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MSC->IFC = flags;
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}
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/***************************************************************************//**
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* @brief
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* Disable one or more MSC interrupts.
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*
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* @param[in] flags
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* MSC interrupt sources to disable. Use a bitwise logic OR combination of
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* valid interrupt flags for the MSC module (MSC_IF_nnn).
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******************************************************************************/
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static __INLINE void MSC_IntDisable(uint32_t flags)
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{
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MSC->IEN &= ~(flags);
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}
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/***************************************************************************//**
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* @brief
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* Enable one or more MSC interrupts.
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*
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* @note
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* Depending on the use, a pending interrupt may already be set prior to
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* enabling the interrupt. Consider using MSC_IntClear() prior to enabling
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* if such a pending interrupt should be ignored.
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*
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* @param[in] flags
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* MSC interrupt sources to enable. Use a bitwise logic OR combination of
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* valid interrupt flags for the MSC module (MSC_IF_nnn).
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******************************************************************************/
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static __INLINE void MSC_IntEnable(uint32_t flags)
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{
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MSC->IEN |= flags;
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}
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/***************************************************************************//**
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* @brief
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* Get pending MSV interrupt flags.
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*
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* @note
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* The event bits are not cleared by the use of this function.
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*
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* @return
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* MSC interrupt sources pending. A bitwise logic OR combination of valid
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* interrupt flags for the MSC module (MSC_IF_nnn).
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******************************************************************************/
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static __INLINE uint32_t MSC_IntGet(void)
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{
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return(MSC->IF);
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}
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/***************************************************************************//**
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* @brief
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* Set one or more pending MSC interrupts from SW.
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*
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* @param[in] flags
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* MSC interrupt sources to set to pending. Use a bitwise logic OR combination of
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* valid interrupt flags for the MSC module (MSC_IF_nnn).
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******************************************************************************/
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static __INLINE void MSC_IntSet(uint32_t flags)
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{
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MSC->IFS = flags;
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}
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#if defined(_EFM32_TINY_FAMILY) || defined(_EFM32_GIANT_FAMILY)
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/***************************************************************************//**
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* @brief
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* Starts measuring cache hit ratio.
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* @details
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* This function starts the performance counters. It is defined inline to
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* minimize the impact of this code on the measurement itself.
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******************************************************************************/
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static __INLINE void MSC_StartCacheMeasurement(void)
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{
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/* Clear CMOF and CHOF to catch these later */
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MSC->IFC = MSC_IF_CHOF | MSC_IF_CMOF;
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/* Start performance counters */
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MSC->CMD = MSC_CMD_STARTPC;
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}
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/***************************************************************************//**
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* @brief
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* Stops measuring the hit rate.
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* @note
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* This function is defined inline to minimize the impact of this
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* code on the measurement itself.
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* This code only works for relatively short sections of code. If you wish
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* to measure longer sections of code you need to implement a IRQ Handler for
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* The CHOF and CMOF overflow interrupts. Theses overflows needs to be
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* counted and included in the total.
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* The functions can then be implemented as follows:
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* @verbatim
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* volatile uint32_t hitOverflows
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* volatile uint32_t missOverflows
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*
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* void MSC_IRQHandler(void)
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* {
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* uint32_t flags;
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* flags = MSC->IF;
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* if (flags & MSC_IF_CHOF)
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* {
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* MSC->IFC = MSC_IF_CHOF;
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* hitOverflows++;
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* }
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* if (flags & MSC_IF_CMOF)
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* {
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* MSC->IFC = MSC_IF_CMOF;
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* missOverflows++;
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* }
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* }
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*
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* void startPerformanceCounters(void)
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* {
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* hitOverflows = 0;
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* missOverflows = 0;
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*
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* MSC_IntEnable(MSC_IF_CHOF | MSC_IF_CMOF);
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* NVIC_EnableIRQ(MSC_IRQn);
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*
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* MSC_StartCacheMeasurement();
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* }
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* @endverbatim
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* @return
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* Returns -1 if there has been no cache accesses.
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* Returns -2 if there has been an overflow in the performance counters.
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* If not, it will return the percentage of hits versus misses.
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******************************************************************************/
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static __INLINE int32_t MSC_GetCacheMeasurement(void)
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{
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int32_t total;
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/* Stop the counter before computing the hit-rate */
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MSC->CMD = MSC_CMD_STOPPC;
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/* Check for overflows in performance counters */
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if (MSC->IF & (MSC_IF_CHOF | MSC_IF_CMOF))
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return -2;
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/* Because the hits and misses are volatile, we need to split this up into
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* two statements to avoid a compiler warning regarding the order of volatile
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* accesses. */
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total = MSC->CACHEHITS;
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total += MSC->CACHEMISSES;
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/* To avoid a division by zero. */
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if (total == 0)
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return -1;
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return (MSC->CACHEHITS * 100) / total;
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}
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/***************************************************************************//**
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* @brief
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* Flush the contents of the instruction cache.
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******************************************************************************/
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static __INLINE void MSC_FlushCache(void)
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{
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MSC->CMD = MSC_CMD_INVCACHE;
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}
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/***************************************************************************//**
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* @brief
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* Enable or disable instruction cache functionality
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* @param[in] enable
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* Enable instruction cache. Default is on.
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******************************************************************************/
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static __INLINE void MSC_EnableCache(bool enable)
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{
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BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_IFCDIS_SHIFT, ~enable);
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}
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/***************************************************************************//**
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* @brief
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* Enable or disable instruction cache functionality in IRQs
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* @param[in] enable
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* Enable instruction cache. Default is on.
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******************************************************************************/
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static __INLINE void MSC_EnableCacheIRQs(bool enable)
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{
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BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_ICCDIS_SHIFT, ~enable);
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}
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/***************************************************************************//**
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* @brief
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* Enable or disable instruction cache flushing when writing to flash
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* @param[in] enable
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* Enable automatic cache flushing. Default is on.
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******************************************************************************/
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static __INLINE void MSC_EnableAutoCacheFlush(bool enable)
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{
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BITBAND_Peripheral(&(MSC->READCTRL), _MSC_READCTRL_AIDIS_SHIFT, ~enable);
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}
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#endif
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#if defined(_EFM32_GIANT_FAMILY)
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/***************************************************************************//**
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* @brief
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* Configure which unit should get priority on system bus.
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* @param[in] mode
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* Unit to prioritize bus accesses for.
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******************************************************************************/
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static __INLINE void MSC_BusStrategy(mscBusStrategy_Typedef mode)
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{
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MSC->READCTRL = (MSC->READCTRL & ~(_MSC_READCTRL_BUSSTRATEGY_MASK))|mode;
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}
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#endif
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#ifdef __CC_ARM /* MDK-ARM compiler */
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msc_Return_TypeDef MSC_WriteWord(uint32_t *address, void const *data, int numBytes);
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msc_Return_TypeDef MSC_ErasePage(uint32_t *startAddress);
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#if defined (_EFM32_GIANT_FAMILY)
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msc_Return_TypeDef MSC_MassErase(void);
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#endif
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#endif /* __CC_ARM */
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#ifdef __ICCARM__ /* IAR compiler */
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__ramfunc msc_Return_TypeDef MSC_WriteWord(uint32_t *address, void const *data, int numBytes);
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__ramfunc msc_Return_TypeDef MSC_ErasePage(uint32_t *startAddress);
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#if defined (_EFM32_GIANT_FAMILY)
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__ramfunc msc_Return_TypeDef MSC_MassErase(void);
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#endif
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#endif /* __ICCARM__ */
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#ifdef __GNUC__ /* GCC based compilers */
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#ifdef __CROSSWORKS_ARM /* Rowley Crossworks */
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msc_Return_TypeDef MSC_WriteWord(uint32_t *address, void const *data, int numBytes) __attribute__ ((section(".fast")));
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msc_Return_TypeDef MSC_ErasePage(uint32_t *startAddress) __attribute__ ((section(".fast")));
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#if defined (_EFM32_GIANT_FAMILY)
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msc_Return_TypeDef MSC_MassErase(void) __attribute__ ((section(".fast")));
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#endif
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#else /* Sourcery G++ */
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msc_Return_TypeDef MSC_WriteWord(uint32_t *address, void const *data, int numBytes) __attribute__ ((section(".ram")));
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msc_Return_TypeDef MSC_ErasePage(uint32_t *startAddress) __attribute__ ((section(".ram")));
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#if defined (_EFM32_GIANT_FAMILY)
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msc_Return_TypeDef MSC_MassErase(void) __attribute__ ((section(".ram")));
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#endif
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#endif /* __GNUC__ */
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#endif /* __CROSSWORKS_ARM */
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/** @} (end addtogroup MSC) */
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/** @} (end addtogroup EFM32_Library) */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __EFM32_MSC_H */
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