462 lines
11 KiB
C
462 lines
11 KiB
C
/* ------------------------------------------
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* Copyright (c) 2016, Synopsys, Inc. All rights reserved.
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1) Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* \version 2016.05
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* \date 2014-07-15
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* \author Wayne Ren(Wei.Ren@synopsys.com)
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--------------------------------------------- */
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/**
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* \file
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* \ingroup ARC_HAL_EXCEPTION_CPU ARC_HAL_EXCEPTION_INTERRUPT
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* \brief header file of exception and interrupt management module
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*/
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#ifndef _ARC_HAL_EXCEPTION_H_
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#define _ARC_HAL_EXCEPTION_H_
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#include "inc/embARC_toolchain.h"
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#include "inc/arc/arc.h"
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#include "inc/arc/arc_builtin.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* \addtogroup ARC_HAL_EXCEPTION_CPU
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* @{
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* \todo need a conf.h from application or board to define the
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* features of processor, such as number of exception, code
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* density and FIQ.
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*/
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#ifndef NUM_EXC_CPU
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#define NUM_EXC_CPU 16 /*!< number of CPU exceptions */
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#endif
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#ifndef NUM_EXC_INT
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#define NUM_EXC_INT 9 /*!< number of interrupt exceptions, defined by users*/
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#endif
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#define NUM_EXC_ALL (NUM_EXC_CPU + NUM_EXC_INT) /*!< total number of exceptions */
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#ifdef ARC_FEATURE_SEC_PRESENT
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typedef struct int_exc_frame {
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uint32_t erbta;
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uint32_t r30; /* r30 is useless, skipped? */
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uint32_t ilink; /* r29 is useless, skipped?*/
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/* r28 is sp, saved other place */
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uint32_t fp; /* r27 */
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uint32_t gp; /* r26 */
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uint32_t r12;
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uint32_t lp_end, lp_start, lp_count;
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#ifdef ARC_FEATURE_CODE_DENSITY
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uint32_t ei, ldi, jli;
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#endif
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uint32_t r0, r1, r2, r3;
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#ifndef ARC_FEATURE_RF16
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uint32_t r4, r5, r6, r7, r8, r9;
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#endif
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uint32_t r10, r11;
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uint32_t blink; /* r31 */
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uint32_t ret;
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uint32_t sec_stat;
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uint32_t status32;
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} EMBARC_PACKED INT_EXC_FRAME;
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#else
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typedef struct int_exc_frame {
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uint32_t erbta;
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uint32_t r30; /* r30 is useless, skipped? */
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uint32_t ilink; /* r29 is useless, skipped?*/
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/* r28 is sp, saved other place */
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uint32_t fp; /* r27 */
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uint32_t gp; /* r26 */
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uint32_t r12;
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uint32_t r0, r1, r2, r3;
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#ifndef ARC_FEATURE_RF16
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uint32_t r4, r5, r6, r7, r8, r9;
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#endif
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uint32_t r10, r11;
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uint32_t blink; /* r31 */
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uint32_t lp_end, lp_start, lp_count;
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#ifdef ARC_FEATURE_CODE_DENSITY
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uint32_t ei, ldi, jli;
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#endif
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uint32_t ret;
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uint32_t status32;
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} EMBARC_PACKED INT_EXC_FRAME;
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#endif
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typedef struct callee_frame {
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#ifndef ARC_FEATURE_RF16
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uint32_t r25;
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uint32_t r24;
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uint32_t r23;
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uint32_t r22;
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uint32_t r21;
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uint32_t r20;
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uint32_t r19;
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uint32_t r18;
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uint32_t r17;
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uint32_t r16;
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#endif
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uint32_t r15;
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uint32_t r14;
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uint32_t r13;
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} EMBARC_PACKED CALLEE_FRAME;
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typedef struct processor_frame {
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CALLEE_FRAME callee_regs;
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INT_EXC_FRAME exc_frame;
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} EMBARC_PACKED PROCESSOR_FRAME;
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#define ARC_PROCESSOR_FRAME_SIZE (sizeof(PROCESSOR_FRAME) / sizeof(uint32_t))
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#define ARC_EXC_FRAME_SIZE (sizeof(INT_EXC_FRAME) / sizeof(uint32_t))
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#define ARC_CALLEE_FRAME_SIZE (sizeof(CALLEE_FRAME) / sizeof(uint32_t))
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extern uint32_t exc_nest_count;
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/**
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* \brief write the exception vector base
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*
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* \param[in] vec_base the target vector base
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*/
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Inline void arc_vector_base_write(const void * vec_base)
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{
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_arc_aux_write(AUX_INT_VECT_BASE, (uint32_t)vec_base);
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}
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/**
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* \brief read current exception vector base
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*
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* \returns exception vector base (uint32_t)
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*/
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Inline uint32_t arc_vector_base_read(void)
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{
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return _arc_aux_read(AUX_INT_VECT_BASE);
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}
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/**
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* \brief sense whether in exc/interrupt processing
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*
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* \retval 0 not in exc/interrupt processing
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* \retval 1 in exc/interrupt processing
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*/
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Inline uint32_t exc_sense(void)
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{
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return (exc_nest_count > 0U);
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}
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/** @}*/
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/**
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* \addtogroup ARC_HAL_EXCEPTION_INTERRUPT
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* @{
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*/
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#ifndef INT_PRI_MIN
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#define INT_PRI_MIN (-2) /*!< the minimum interrupt priority */
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#endif
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#define INT_PRI_MAX (-1) /*!< the maximum interrupt priority */
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/**
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* \brief disable the specific interrupt
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*
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* \param[in] intno interrupt number
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*/
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Inline void arc_int_disable(const uint32_t intno)
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{
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_arc_aux_write(AUX_IRQ_SELECT, intno);
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_arc_aux_write(AUX_IRQ_ENABLE, 0);
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}
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/**
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* \brief enable the specific int
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*
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* \param[in] intno interrupt number
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*/
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Inline void arc_int_enable(const uint32_t intno)
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{
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_arc_aux_write(AUX_IRQ_SELECT, intno);
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_arc_aux_write(AUX_IRQ_ENABLE, 1);
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}
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/**
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* \brief check whether the specific int is enabled
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*
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* \param[in] intno interrupt number
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* \return 0 disabled, 1 enabled
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*/
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Inline uint32_t arc_int_enabled(const uint32_t intno)
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{
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_arc_aux_write(AUX_IRQ_SELECT, intno);
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return _arc_aux_read(AUX_IRQ_ENABLE);
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}
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/**
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* \brief get the interrupt priority mask
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*
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* \returns interrupt priority mask, negative num
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*/
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Inline uint32_t arc_int_ipm_get(void)
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{
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return ((_arc_aux_read(AUX_STATUS32) >> 1) & 0x0f);
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}
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/**
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* \brief set the interrupt priority mask
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*
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* \param[in] intpri interrupt priority
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*/
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Inline void arc_int_ipm_set(uint32_t intpri)
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{
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volatile uint32_t status;
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status = _arc_aux_read(AUX_STATUS32) & ~0x1e;
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status = status | ((intpri << 1) & 0x1e);
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/* sr cannot write AUX_STATUS32 */
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Asm("kflag %0"::"ir"(status));
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}
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/**
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* \brief get current interrupt priority mask
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*
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* \param[in] intno interrupt number
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*/
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Inline uint32_t arc_int_pri_get(const uint32_t intno)
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{
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_arc_aux_write(AUX_IRQ_SELECT, intno);
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return _arc_aux_read(AUX_IRQ_PRIORITY);
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}
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/**
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* \brief set interrupt priority
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*
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* \param[in] intno interrupt number
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* \param[in] intpri interrupt priority
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*/
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Inline void arc_int_pri_set(const uint32_t intno, uint32_t intpri)
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{
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_arc_aux_write(AUX_IRQ_SELECT, intno);
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_arc_aux_write(AUX_IRQ_PRIORITY, intpri | (_arc_aux_read(AUX_IRQ_PRIORITY) & 0xfffffff0));
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}
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/**
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* \brief set interrupt secure or not secure
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*
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* \param[in] intno interrupt number
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* \param[in] secure, 0 for normal, >0 for secure
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*/
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Inline void arc_int_secure_set(const uint32_t intno, uint32_t secure)
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{
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_arc_aux_write(AUX_IRQ_SELECT, intno);
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if (secure) {
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_arc_aux_write(AUX_IRQ_PRIORITY, _arc_aux_read(AUX_IRQ_PRIORITY) |
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(1 << AUX_IRQ_PRIORITY_BIT_S));
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} else {
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_arc_aux_write(AUX_IRQ_PRIORITY, _arc_aux_read(AUX_IRQ_PRIORITY) & 0xf);
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}
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}
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/**
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* \brief probe the pending status of interrupt
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*
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* \param[in] intno interrupt number
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*
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* \returns 1 pending, 0 no pending
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*/
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Inline uint32_t arc_int_probe(const uint32_t intno)
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{
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_arc_aux_write(AUX_IRQ_SELECT, intno);
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return _arc_aux_read(AUX_IRQ_PENDING);
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}
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/**
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* \brief trigger the interrupt in software
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*
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* \param[in] intno interrupt number
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*/
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Inline void arc_int_sw_trigger(const uint32_t intno)
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{
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_arc_aux_write(AUX_IRQ_HINT, intno);
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}
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/**
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* \brief config the interrupt level triggered or pulse triggered
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*
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* \param[in] intno interrupt number
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* \param[in] level, 0-level trigger, 1-pluse triggered
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*/
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Inline void arc_int_level_config(const uint32_t intno, const uint32_t level)
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{
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_arc_aux_write(AUX_IRQ_SELECT, intno);
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_arc_aux_write(AUX_IRQ_TRIGGER, level);
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}
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/**
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* \brief lock cpu, disable interrupts
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*/
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Inline void arc_lock(void)
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{
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Asm("clri");
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Asm("":::"memory");
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}
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/**
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* \brief unlock cpu, enable interrupts to happen
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*/
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Inline void arc_unlock(void)
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{
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Asm("":::"memory");
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Asm("seti");
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}
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/**
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* \brief lock cpu and staus
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*
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* \returns cpu status
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*/
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Inline uint32_t arc_lock_save(void)
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{
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return _arc_clri();
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}
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/**
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* \brief unlock cpu with the specific status
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*
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* \param[in] status cpu status saved by cpu_lock_save
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*/
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Inline void arc_unlock_restore(const uint32_t status)
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{
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_arc_seti(status);
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}
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/** @}*/
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/**
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* \addtogroup ARC_HAL_EXCEPTION_CPU
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* @{
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*/
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/**
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* \typedef EXC_ENTRY
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* \brief the data type for exception entry
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*/
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typedef void (*EXC_ENTRY) (void);
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/**
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* \typedef EXC_HANDLER
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* \brief the data type for exception handler
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*/
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typedef void (*EXC_HANDLER) (void *exc_frame);
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/** @}*/
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/**
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* \ingroup ARC_HAL_EXCEPTION_INTERRUPT
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* \typedef INT_HANDLER
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* \brief the data type for interrupt handler
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*/
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typedef void (*INT_HANDLER) (void *ptr);
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extern EXC_ENTRY exc_entry_table[NUM_EXC_ALL];
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extern EXC_HANDLER exc_int_handler_table[NUM_EXC_ALL];
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/** \ingroup ARC_HAL_EXCEPTION_CPU
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* @{
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*/
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/**
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* \fn _arc_reset
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* \brief the reset entry
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*/
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extern void _arc_reset(void);
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/**
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* \fn exc_entry_cpu
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* \brief the default CPU exception entry
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*/
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extern void exc_entry_cpu(void);
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/**
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* \fn exc_entry_firq
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* \brief the fast interrupt exception entry
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*/
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extern void exc_entry_firq(void);
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/**
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* \fn exc_entry_int
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* \brief the interrupt exception entry
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*/
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extern void exc_entry_int(void);
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/** @}*/
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/* excetpion related apis */
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extern void exc_int_init(void);
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extern int32_t exc_entry_install(const uint32_t excno, EXC_ENTRY entry);
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extern EXC_ENTRY exc_entry_get(const uint32_t excno);
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extern int32_t exc_handler_install(const uint32_t excno, EXC_HANDLER handler);
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extern EXC_HANDLER exc_handler_get(const uint32_t excno);
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/* interrupt related apis */
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extern int32_t int_disable(const uint32_t intno);
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extern int32_t int_enable(const uint32_t intno);
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extern int32_t int_enabled(const uint32_t intno);
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extern int32_t int_ipm_get(void);
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extern int32_t int_ipm_set(int32_t intpri);
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extern int32_t int_pri_get(const uint32_t intno);
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extern int32_t int_pri_set(const uint32_t intno, int32_t intpri);
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extern int32_t int_probe(const uint32_t intno);
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extern int32_t int_sw_trigger(const uint32_t intno);
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extern int32_t int_level_config(const uint32_t intno, const uint32_t level);
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extern void cpu_lock(void);
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extern void cpu_unlock(void);
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extern uint32_t cpu_lock_save(void);
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extern void cpu_unlock_restore(const uint32_t status);
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extern int32_t int_handler_install(const uint32_t intno, INT_HANDLER handler);
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extern INT_HANDLER int_handler_get(const uint32_t intno);
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extern int32_t int_secure_set(const uint32_t intno, uint32_t secure);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ARC_HAL_EXCEPTION_H_*/
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