261 lines
7.2 KiB
C
261 lines
7.2 KiB
C
/*
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* Copyright (C) 2022-2024, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-04-28 CDT first version
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* 2022-06-08 xiaoxiaolisunny add hc32f460 series
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* 2022-06-14 CDT fix a bug of internal trigger
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*/
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#include <board.h>
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#include <drivers/adc.h>
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#include <drv_adc.h>
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#include <drv_config.h>
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#define DBG_TAG "drv.adc"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#ifdef RT_USING_ADC
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typedef struct
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{
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struct rt_adc_device rt_adc;
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CM_ADC_TypeDef *instance;
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struct adc_dev_init_params init;
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} adc_device;
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#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
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static adc_device _g_adc_dev_array[] =
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{
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#ifdef BSP_USING_ADC1
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{
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{0},
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CM_ADC1,
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ADC1_INIT_PARAMS,
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},
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#endif
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#ifdef BSP_USING_ADC2
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{
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{0},
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CM_ADC2,
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ADC2_INIT_PARAMS,
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},
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#endif
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#ifdef BSP_USING_ADC3
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{
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{0},
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CM_ADC3,
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ADC3_INIT_PARAMS,
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},
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#endif
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};
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static void _adc_internal_trigger0_set(adc_device *p_adc_dev)
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{
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uint32_t u32TriggerSel;
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rt_bool_t is_internal_trig0_enabled = (p_adc_dev->init.hard_trig_src == ADC_HARDTRIG_EVT0 || p_adc_dev->init.hard_trig_src == ADC_HARDTRIG_EVT0_EVT1);
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if (is_internal_trig0_enabled == RT_FALSE)
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{
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return;
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}
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switch ((rt_uint32_t)p_adc_dev->instance)
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{
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case (rt_uint32_t)CM_ADC1:
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u32TriggerSel = AOS_ADC1_0;
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break;
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case (rt_uint32_t)CM_ADC2:
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u32TriggerSel = AOS_ADC2_0;
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break;
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case (rt_uint32_t)CM_ADC3:
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u32TriggerSel = AOS_ADC3_0;
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break;
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default:
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break;
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}
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AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg0_enable);
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AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)p_adc_dev->init.internal_trig0_comtrg1_enable);
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AOS_SetTriggerEventSrc(u32TriggerSel, p_adc_dev->init.internal_trig0_sel);
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}
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static void _adc_internal_trigger1_set(adc_device *p_adc_dev)
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{
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uint32_t u32TriggerSel;
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rt_bool_t is_internal_trig1_enabled = (p_adc_dev->init.hard_trig_src == ADC_HARDTRIG_EVT1 || p_adc_dev->init.hard_trig_src == ADC_HARDTRIG_EVT0_EVT1);
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if (is_internal_trig1_enabled == RT_FALSE)
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{
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return;
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}
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switch ((rt_uint32_t)p_adc_dev->instance)
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{
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case (rt_uint32_t)CM_ADC1:
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u32TriggerSel = AOS_ADC1_1;
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break;
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case (rt_uint32_t)CM_ADC2:
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u32TriggerSel = AOS_ADC2_1;
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break;
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case (rt_uint32_t)CM_ADC3:
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u32TriggerSel = AOS_ADC3_1;
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break;
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default:
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break;
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}
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AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG1, (en_functional_state_t)p_adc_dev->init.internal_trig1_comtrg0_enable);
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AOS_CommonTriggerCmd(u32TriggerSel, AOS_COMM_TRIG2, (en_functional_state_t)p_adc_dev->init.internal_trig1_comtrg1_enable);
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AOS_SetTriggerEventSrc(u32TriggerSel, p_adc_dev->init.internal_trig1_sel);
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}
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static rt_err_t _adc_enable(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled)
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{
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adc_device *p_adc_dev = rt_container_of(device, adc_device, rt_adc);
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ADC_ChCmd(p_adc_dev->instance, ADC_SEQ_A, channel, (en_functional_state_t)enabled);
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return 0;
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}
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static rt_err_t _adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
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{
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rt_err_t rt_ret = -RT_ERROR;
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if (!value)
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{
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return -RT_EINVAL;
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}
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adc_device *p_adc_dev = rt_container_of(device, adc_device, rt_adc);
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if (p_adc_dev->init.hard_trig_enable == RT_FALSE && p_adc_dev->instance->STR == 0)
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{
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ADC_Start(p_adc_dev->instance);
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}
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uint32_t start_time = rt_tick_get();
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do
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{
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if (ADC_GetStatus(p_adc_dev->instance, ADC_FLAG_EOCA) == SET)
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{
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ADC_ClearStatus(p_adc_dev->instance, ADC_FLAG_EOCA);
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rt_ret = LL_OK;
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break;
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}
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}
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while ((rt_tick_get() - start_time) < p_adc_dev->init.eoc_poll_time_max);
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if (rt_ret == LL_OK)
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{
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/* Get any ADC value of sequence A channel that needed. */
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*value = ADC_GetValue(p_adc_dev->instance, channel);
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}
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return rt_ret;
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}
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static rt_uint8_t _adc_get_resolution(struct rt_adc_device *device)
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{
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rt_uint8_t resolution = 0;
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rt_uint16_t accsel;
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adc_device *p_adc_dev = rt_container_of(device, adc_device, rt_adc);
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accsel = ADC_GetResolution(p_adc_dev->instance);
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switch (accsel)
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{
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case ADC_RESOLUTION_12BIT:
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resolution = 12;
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break;
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case ADC_RESOLUTION_10BIT:
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resolution = 10;
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break;
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case ADC_RESOLUTION_8BIT:
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resolution = 8;
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break;
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default:
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break;
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}
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return resolution;
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}
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static rt_int16_t _adc_get_vref(struct rt_adc_device *device)
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{
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rt_int16_t vref = 0;
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adc_device *p_adc_dev = rt_container_of(device, adc_device, rt_adc);
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vref = p_adc_dev->init.vref;
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return vref;
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}
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static struct rt_adc_ops _g_adc_ops =
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{
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_adc_enable,
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_adc_convert,
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_adc_get_resolution,
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_adc_get_vref
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};
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static void _adc_clock_enable(void)
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{
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#if defined(BSP_USING_ADC1)
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FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC1, ENABLE);
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#endif
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#if defined(BSP_USING_ADC2)
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FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC2, ENABLE);
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#endif
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#if defined(BSP_USING_ADC3)
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FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_ADC3, ENABLE);
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#endif
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}
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extern rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx);
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int rt_hw_adc_init(void)
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{
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int ret = RT_EOK, i = 0;
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stc_adc_init_t stcAdcInit = {0};
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int32_t ll_ret = 0;
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_adc_clock_enable();
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uint32_t dev_cnt = sizeof(_g_adc_dev_array) / sizeof(_g_adc_dev_array[0]);
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for (; i < dev_cnt; i++)
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{
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ADC_DeInit(_g_adc_dev_array[i].instance);
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/* Initializes ADC. */
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stcAdcInit.u16Resolution = _g_adc_dev_array[i].init.resolution;
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stcAdcInit.u16DataAlign = _g_adc_dev_array[i].init.data_align;
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stcAdcInit.u16ScanMode = (_g_adc_dev_array[i].init.continue_conv_mode_enable) ? ADC_MD_SEQA_CONT : ADC_MD_SEQA_SINGLESHOT;
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ll_ret = ADC_Init((void *)_g_adc_dev_array[i].instance, &stcAdcInit);
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if (ll_ret != LL_OK)
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{
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ret = -RT_ERROR;
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break;
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}
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ADC_TriggerCmd(_g_adc_dev_array[i].instance, ADC_SEQ_A, (en_functional_state_t)_g_adc_dev_array[i].init.hard_trig_enable);
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ADC_TriggerConfig(_g_adc_dev_array[i].instance, ADC_SEQ_A, _g_adc_dev_array[i].init.hard_trig_src);
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if (_g_adc_dev_array[i].init.hard_trig_enable && _g_adc_dev_array[i].init.hard_trig_src != ADC_HARDTRIG_ADTRG_PIN)
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{
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_adc_internal_trigger0_set(&_g_adc_dev_array[i]);
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_adc_internal_trigger1_set(&_g_adc_dev_array[i]);
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}
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rt_hw_board_adc_init((void *)_g_adc_dev_array[i].instance);
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ret = rt_hw_adc_register(&_g_adc_dev_array[i].rt_adc, \
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(const char *)_g_adc_dev_array[i].init.name, \
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&_g_adc_ops, (void *)_g_adc_dev_array[i].instance);
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if (ret != RT_EOK)
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{
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LOG_E("failed register %s, err=%d", _g_adc_dev_array[i].init.name, ret);
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}
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}
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return ret;
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}
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INIT_DEVICE_EXPORT(rt_hw_adc_init);
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#endif
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#endif /* RT_USING_ADC */
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