567 lines
21 KiB
C
567 lines
21 KiB
C
/*
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* Copyright (c) 2014, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* THIS SOFTWARE IS PROVIDED BY FREESCALE "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
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* SHALL FREESCALE BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
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* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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/*
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* WARNING! DO NOT EDIT THIS FILE DIRECTLY!
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*
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* This file was generated automatically and any changes may be lost.
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*/
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#ifndef __HW_SMC_REGISTERS_H__
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#define __HW_SMC_REGISTERS_H__
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#include "regs.h"
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/*
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* MK64F12 SMC
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*
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* System Mode Controller
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*
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* Registers defined in this header file:
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* - HW_SMC_PMPROT - Power Mode Protection register
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* - HW_SMC_PMCTRL - Power Mode Control register
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* - HW_SMC_VLLSCTRL - VLLS Control register
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* - HW_SMC_PMSTAT - Power Mode Status register
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*
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* - hw_smc_t - Struct containing all module registers.
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*/
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//! @name Module base addresses
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//@{
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#ifndef REGS_SMC_BASE
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#define HW_SMC_INSTANCE_COUNT (1U) //!< Number of instances of the SMC module.
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#define REGS_SMC_BASE (0x4007E000U) //!< Base address for SMC.
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_SMC_PMPROT - Power Mode Protection register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_SMC_PMPROT - Power Mode Protection register (RW)
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*
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* Reset value: 0x00U
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*
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* This register provides protection for entry into any low-power run or stop
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* mode. The enabling of the low-power run or stop mode occurs by configuring the
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* Power Mode Control register (PMCTRL). The PMPROT register can be written only
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* once after any system reset. If the MCU is configured for a disallowed or
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* reserved power mode, the MCU remains in its current power mode. For example, if the
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* MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using
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* PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is
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* still in Normal Run mode. This register is reset on Chip Reset not VLLS and by
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* reset types that trigger Chip Reset not VLLS. It is unaffected by reset types
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* that do not trigger Chip Reset not VLLS. See the Reset section details for more
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* information.
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*/
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typedef union _hw_smc_pmprot
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{
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uint8_t U;
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struct _hw_smc_pmprot_bitfields
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{
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uint8_t RESERVED0 : 1; //!< [0]
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uint8_t AVLLS : 1; //!< [1] Allow Very-Low-Leakage Stop Mode
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uint8_t RESERVED1 : 1; //!< [2]
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uint8_t ALLS : 1; //!< [3] Allow Low-Leakage Stop Mode
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uint8_t RESERVED2 : 1; //!< [4]
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uint8_t AVLP : 1; //!< [5] Allow Very-Low-Power Modes
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uint8_t RESERVED3 : 2; //!< [7:6]
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} B;
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} hw_smc_pmprot_t;
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#endif
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/*!
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* @name Constants and macros for entire SMC_PMPROT register
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*/
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//@{
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#define HW_SMC_PMPROT_ADDR (REGS_SMC_BASE + 0x0U)
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#ifndef __LANGUAGE_ASM__
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#define HW_SMC_PMPROT (*(__IO hw_smc_pmprot_t *) HW_SMC_PMPROT_ADDR)
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#define HW_SMC_PMPROT_RD() (HW_SMC_PMPROT.U)
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#define HW_SMC_PMPROT_WR(v) (HW_SMC_PMPROT.U = (v))
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#define HW_SMC_PMPROT_SET(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() | (v)))
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#define HW_SMC_PMPROT_CLR(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() & ~(v)))
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#define HW_SMC_PMPROT_TOG(v) (HW_SMC_PMPROT_WR(HW_SMC_PMPROT_RD() ^ (v)))
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#endif
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//@}
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/*
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* Constants & macros for individual SMC_PMPROT bitfields
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*/
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/*!
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* @name Register SMC_PMPROT, field AVLLS[1] (RW)
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*
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* Provided the appropriate control bits are set up in PMCTRL, this write once
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* bit allows the MCU to enter any very-low-leakage stop mode (VLLSx).
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*
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* Values:
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* - 0 - Any VLLSx mode is not allowed
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* - 1 - Any VLLSx mode is allowed
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*/
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//@{
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#define BP_SMC_PMPROT_AVLLS (1U) //!< Bit position for SMC_PMPROT_AVLLS.
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#define BM_SMC_PMPROT_AVLLS (0x02U) //!< Bit mask for SMC_PMPROT_AVLLS.
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#define BS_SMC_PMPROT_AVLLS (1U) //!< Bit field size in bits for SMC_PMPROT_AVLLS.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the SMC_PMPROT_AVLLS field.
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#define BR_SMC_PMPROT_AVLLS (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLLS))
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#endif
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//! @brief Format value for bitfield SMC_PMPROT_AVLLS.
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#define BF_SMC_PMPROT_AVLLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_AVLLS), uint8_t) & BM_SMC_PMPROT_AVLLS)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the AVLLS field to a new value.
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#define BW_SMC_PMPROT_AVLLS(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLLS) = (v))
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#endif
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//@}
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/*!
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* @name Register SMC_PMPROT, field ALLS[3] (RW)
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*
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* Provided the appropriate control bits are set up in PMCTRL, this write-once
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* field allows the MCU to enter any low-leakage stop mode (LLS).
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*
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* Values:
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* - 0 - LLS is not allowed
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* - 1 - LLS is allowed
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*/
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//@{
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#define BP_SMC_PMPROT_ALLS (3U) //!< Bit position for SMC_PMPROT_ALLS.
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#define BM_SMC_PMPROT_ALLS (0x08U) //!< Bit mask for SMC_PMPROT_ALLS.
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#define BS_SMC_PMPROT_ALLS (1U) //!< Bit field size in bits for SMC_PMPROT_ALLS.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the SMC_PMPROT_ALLS field.
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#define BR_SMC_PMPROT_ALLS (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_ALLS))
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#endif
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//! @brief Format value for bitfield SMC_PMPROT_ALLS.
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#define BF_SMC_PMPROT_ALLS(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_ALLS), uint8_t) & BM_SMC_PMPROT_ALLS)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the ALLS field to a new value.
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#define BW_SMC_PMPROT_ALLS(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_ALLS) = (v))
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#endif
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//@}
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/*!
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* @name Register SMC_PMPROT, field AVLP[5] (RW)
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*
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* Provided the appropriate control bits are set up in PMCTRL, this write-once
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* field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS).
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*
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* Values:
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* - 0 - VLPR, VLPW, and VLPS are not allowed.
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* - 1 - VLPR, VLPW, and VLPS are allowed.
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*/
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//@{
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#define BP_SMC_PMPROT_AVLP (5U) //!< Bit position for SMC_PMPROT_AVLP.
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#define BM_SMC_PMPROT_AVLP (0x20U) //!< Bit mask for SMC_PMPROT_AVLP.
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#define BS_SMC_PMPROT_AVLP (1U) //!< Bit field size in bits for SMC_PMPROT_AVLP.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the SMC_PMPROT_AVLP field.
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#define BR_SMC_PMPROT_AVLP (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLP))
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#endif
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//! @brief Format value for bitfield SMC_PMPROT_AVLP.
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#define BF_SMC_PMPROT_AVLP(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMPROT_AVLP), uint8_t) & BM_SMC_PMPROT_AVLP)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the AVLP field to a new value.
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#define BW_SMC_PMPROT_AVLP(v) (BITBAND_ACCESS8(HW_SMC_PMPROT_ADDR, BP_SMC_PMPROT_AVLP) = (v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_SMC_PMCTRL - Power Mode Control register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_SMC_PMCTRL - Power Mode Control register (RW)
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*
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* Reset value: 0x00U
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*
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* The PMCTRL register controls entry into low-power Run and Stop modes,
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* provided that the selected power mode is allowed via an appropriate setting of the
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* protection (PMPROT) register. This register is reset on Chip POR not VLLS and by
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* reset types that trigger Chip POR not VLLS. It is unaffected by reset types
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* that do not trigger Chip POR not VLLS. See the Reset section details for more
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* information.
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*/
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typedef union _hw_smc_pmctrl
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{
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uint8_t U;
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struct _hw_smc_pmctrl_bitfields
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{
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uint8_t STOPM : 3; //!< [2:0] Stop Mode Control
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uint8_t STOPA : 1; //!< [3] Stop Aborted
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uint8_t RESERVED0 : 1; //!< [4]
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uint8_t RUNM : 2; //!< [6:5] Run Mode Control
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uint8_t LPWUI : 1; //!< [7] Low-Power Wake Up On Interrupt
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} B;
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} hw_smc_pmctrl_t;
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#endif
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/*!
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* @name Constants and macros for entire SMC_PMCTRL register
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*/
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//@{
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#define HW_SMC_PMCTRL_ADDR (REGS_SMC_BASE + 0x1U)
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#ifndef __LANGUAGE_ASM__
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#define HW_SMC_PMCTRL (*(__IO hw_smc_pmctrl_t *) HW_SMC_PMCTRL_ADDR)
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#define HW_SMC_PMCTRL_RD() (HW_SMC_PMCTRL.U)
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#define HW_SMC_PMCTRL_WR(v) (HW_SMC_PMCTRL.U = (v))
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#define HW_SMC_PMCTRL_SET(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() | (v)))
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#define HW_SMC_PMCTRL_CLR(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() & ~(v)))
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#define HW_SMC_PMCTRL_TOG(v) (HW_SMC_PMCTRL_WR(HW_SMC_PMCTRL_RD() ^ (v)))
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#endif
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//@}
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/*
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* Constants & macros for individual SMC_PMCTRL bitfields
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*/
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/*!
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* @name Register SMC_PMCTRL, field STOPM[2:0] (RW)
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*
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* When written, controls entry into the selected stop mode when Sleep-Now or
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* Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are
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* blocked if the protection level has not been enabled using the PMPROT register.
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* After any system reset, this field is cleared by hardware on any successful write
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* to the PMPROT register. When set to VLLSx, the VLLSM field in the VLLSCTRL
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* register is used to further select the particular VLLS submode which will be
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* entered.
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*
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* Values:
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* - 000 - Normal Stop (STOP)
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* - 001 - Reserved
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* - 010 - Very-Low-Power Stop (VLPS)
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* - 011 - Low-Leakage Stop (LLS)
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* - 100 - Very-Low-Leakage Stop (VLLSx)
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* - 101 - Reserved
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* - 110 - Reseved
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* - 111 - Reserved
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*/
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//@{
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#define BP_SMC_PMCTRL_STOPM (0U) //!< Bit position for SMC_PMCTRL_STOPM.
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#define BM_SMC_PMCTRL_STOPM (0x07U) //!< Bit mask for SMC_PMCTRL_STOPM.
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#define BS_SMC_PMCTRL_STOPM (3U) //!< Bit field size in bits for SMC_PMCTRL_STOPM.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the SMC_PMCTRL_STOPM field.
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#define BR_SMC_PMCTRL_STOPM (HW_SMC_PMCTRL.B.STOPM)
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#endif
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//! @brief Format value for bitfield SMC_PMCTRL_STOPM.
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#define BF_SMC_PMCTRL_STOPM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_STOPM), uint8_t) & BM_SMC_PMCTRL_STOPM)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the STOPM field to a new value.
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#define BW_SMC_PMCTRL_STOPM(v) (HW_SMC_PMCTRL_WR((HW_SMC_PMCTRL_RD() & ~BM_SMC_PMCTRL_STOPM) | BF_SMC_PMCTRL_STOPM(v)))
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#endif
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//@}
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/*!
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* @name Register SMC_PMCTRL, field STOPA[3] (RO)
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*
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* When set, this read-only status bit indicates an interrupt or reset occured
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* during the previous stop mode entry sequence, preventing the system from
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* entering that mode. This field is cleared by hardware at the beginning of any stop
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* mode entry sequence and is set if the sequence was aborted.
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*
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* Values:
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* - 0 - The previous stop mode entry was successsful.
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* - 1 - The previous stop mode entry was aborted.
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*/
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//@{
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#define BP_SMC_PMCTRL_STOPA (3U) //!< Bit position for SMC_PMCTRL_STOPA.
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#define BM_SMC_PMCTRL_STOPA (0x08U) //!< Bit mask for SMC_PMCTRL_STOPA.
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#define BS_SMC_PMCTRL_STOPA (1U) //!< Bit field size in bits for SMC_PMCTRL_STOPA.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the SMC_PMCTRL_STOPA field.
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#define BR_SMC_PMCTRL_STOPA (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_STOPA))
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#endif
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//@}
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/*!
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* @name Register SMC_PMCTRL, field RUNM[6:5] (RW)
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*
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* When written, causes entry into the selected run mode. Writes to this field
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* are blocked if the protection level has not been enabled using the PMPROT
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* register. RUNM may be set to VLPR only when PMSTAT=RUN. After being written to
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* VLPR, RUNM should not be written back to RUN until PMSTAT=VLPR.
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*
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* Values:
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* - 00 - Normal Run mode (RUN)
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* - 01 - Reserved
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* - 10 - Very-Low-Power Run mode (VLPR)
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* - 11 - Reserved
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*/
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//@{
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#define BP_SMC_PMCTRL_RUNM (5U) //!< Bit position for SMC_PMCTRL_RUNM.
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#define BM_SMC_PMCTRL_RUNM (0x60U) //!< Bit mask for SMC_PMCTRL_RUNM.
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#define BS_SMC_PMCTRL_RUNM (2U) //!< Bit field size in bits for SMC_PMCTRL_RUNM.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the SMC_PMCTRL_RUNM field.
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#define BR_SMC_PMCTRL_RUNM (HW_SMC_PMCTRL.B.RUNM)
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#endif
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//! @brief Format value for bitfield SMC_PMCTRL_RUNM.
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#define BF_SMC_PMCTRL_RUNM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_RUNM), uint8_t) & BM_SMC_PMCTRL_RUNM)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the RUNM field to a new value.
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#define BW_SMC_PMCTRL_RUNM(v) (HW_SMC_PMCTRL_WR((HW_SMC_PMCTRL_RD() & ~BM_SMC_PMCTRL_RUNM) | BF_SMC_PMCTRL_RUNM(v)))
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#endif
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//@}
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/*!
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* @name Register SMC_PMCTRL, field LPWUI[7] (RW)
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*
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* Causes the SMC to exit to normal RUN mode when any active MCU interrupt
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* occurs while in a VLP mode (VLPR, VLPW or VLPS). If VLPS mode was entered directly
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* from RUN mode, the SMC will always exit back to normal RUN mode regardless of
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* the LPWUI setting. LPWUI must be modified only while the system is in RUN
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* mode, that is, when PMSTAT=RUN.
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*
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* Values:
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* - 0 - The system remains in a VLP mode on an interrupt
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* - 1 - The system exits to Normal RUN mode on an interrupt
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*/
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//@{
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#define BP_SMC_PMCTRL_LPWUI (7U) //!< Bit position for SMC_PMCTRL_LPWUI.
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#define BM_SMC_PMCTRL_LPWUI (0x80U) //!< Bit mask for SMC_PMCTRL_LPWUI.
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#define BS_SMC_PMCTRL_LPWUI (1U) //!< Bit field size in bits for SMC_PMCTRL_LPWUI.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the SMC_PMCTRL_LPWUI field.
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#define BR_SMC_PMCTRL_LPWUI (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_LPWUI))
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#endif
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//! @brief Format value for bitfield SMC_PMCTRL_LPWUI.
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#define BF_SMC_PMCTRL_LPWUI(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_PMCTRL_LPWUI), uint8_t) & BM_SMC_PMCTRL_LPWUI)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the LPWUI field to a new value.
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#define BW_SMC_PMCTRL_LPWUI(v) (BITBAND_ACCESS8(HW_SMC_PMCTRL_ADDR, BP_SMC_PMCTRL_LPWUI) = (v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_SMC_VLLSCTRL - VLLS Control register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_SMC_VLLSCTRL - VLLS Control register (RW)
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*
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* Reset value: 0x03U
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*
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* The VLLSCTRL register controls features related to VLLS modes. This register
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* is reset on Chip POR not VLLS and by reset types that trigger Chip POR not
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* VLLS. It is unaffected by reset types that do not trigger Chip POR not VLLS. See
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* the Reset section details for more information.
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*/
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typedef union _hw_smc_vllsctrl
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{
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uint8_t U;
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struct _hw_smc_vllsctrl_bitfields
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{
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uint8_t VLLSM : 3; //!< [2:0] VLLS Mode Control
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uint8_t RESERVED0 : 2; //!< [4:3]
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uint8_t PORPO : 1; //!< [5] POR Power Option
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uint8_t RESERVED1 : 2; //!< [7:6]
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} B;
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} hw_smc_vllsctrl_t;
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#endif
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/*!
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* @name Constants and macros for entire SMC_VLLSCTRL register
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*/
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//@{
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#define HW_SMC_VLLSCTRL_ADDR (REGS_SMC_BASE + 0x2U)
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#ifndef __LANGUAGE_ASM__
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#define HW_SMC_VLLSCTRL (*(__IO hw_smc_vllsctrl_t *) HW_SMC_VLLSCTRL_ADDR)
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#define HW_SMC_VLLSCTRL_RD() (HW_SMC_VLLSCTRL.U)
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#define HW_SMC_VLLSCTRL_WR(v) (HW_SMC_VLLSCTRL.U = (v))
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#define HW_SMC_VLLSCTRL_SET(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() | (v)))
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#define HW_SMC_VLLSCTRL_CLR(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() & ~(v)))
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#define HW_SMC_VLLSCTRL_TOG(v) (HW_SMC_VLLSCTRL_WR(HW_SMC_VLLSCTRL_RD() ^ (v)))
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#endif
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//@}
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/*
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* Constants & macros for individual SMC_VLLSCTRL bitfields
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*/
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/*!
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* @name Register SMC_VLLSCTRL, field VLLSM[2:0] (RW)
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*
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* Controls which VLLS sub-mode to enter if STOPM=VLLS.
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*
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* Values:
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* - 000 - VLLS0
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* - 001 - VLLS1
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* - 010 - VLLS2
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* - 011 - VLLS3
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* - 100 - Reserved
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* - 101 - Reserved
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* - 110 - Reserved
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* - 111 - Reserved
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*/
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//@{
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#define BP_SMC_VLLSCTRL_VLLSM (0U) //!< Bit position for SMC_VLLSCTRL_VLLSM.
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#define BM_SMC_VLLSCTRL_VLLSM (0x07U) //!< Bit mask for SMC_VLLSCTRL_VLLSM.
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#define BS_SMC_VLLSCTRL_VLLSM (3U) //!< Bit field size in bits for SMC_VLLSCTRL_VLLSM.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the SMC_VLLSCTRL_VLLSM field.
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#define BR_SMC_VLLSCTRL_VLLSM (HW_SMC_VLLSCTRL.B.VLLSM)
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#endif
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//! @brief Format value for bitfield SMC_VLLSCTRL_VLLSM.
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#define BF_SMC_VLLSCTRL_VLLSM(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_VLLSCTRL_VLLSM), uint8_t) & BM_SMC_VLLSCTRL_VLLSM)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the VLLSM field to a new value.
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#define BW_SMC_VLLSCTRL_VLLSM(v) (HW_SMC_VLLSCTRL_WR((HW_SMC_VLLSCTRL_RD() & ~BM_SMC_VLLSCTRL_VLLSM) | BF_SMC_VLLSCTRL_VLLSM(v)))
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#endif
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//@}
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/*!
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* @name Register SMC_VLLSCTRL, field PORPO[5] (RW)
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*
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* Controls whether the POR detect circuit (for brown-out detection) is enabled
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* in VLLS0 mode.
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*
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* Values:
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* - 0 - POR detect circuit is enabled in VLLS0.
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* - 1 - POR detect circuit is disabled in VLLS0.
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*/
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//@{
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#define BP_SMC_VLLSCTRL_PORPO (5U) //!< Bit position for SMC_VLLSCTRL_PORPO.
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#define BM_SMC_VLLSCTRL_PORPO (0x20U) //!< Bit mask for SMC_VLLSCTRL_PORPO.
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#define BS_SMC_VLLSCTRL_PORPO (1U) //!< Bit field size in bits for SMC_VLLSCTRL_PORPO.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the SMC_VLLSCTRL_PORPO field.
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#define BR_SMC_VLLSCTRL_PORPO (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR, BP_SMC_VLLSCTRL_PORPO))
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#endif
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//! @brief Format value for bitfield SMC_VLLSCTRL_PORPO.
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#define BF_SMC_VLLSCTRL_PORPO(v) (__REG_VALUE_TYPE((__REG_VALUE_TYPE((v), uint8_t) << BP_SMC_VLLSCTRL_PORPO), uint8_t) & BM_SMC_VLLSCTRL_PORPO)
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#ifndef __LANGUAGE_ASM__
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//! @brief Set the PORPO field to a new value.
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#define BW_SMC_VLLSCTRL_PORPO(v) (BITBAND_ACCESS8(HW_SMC_VLLSCTRL_ADDR, BP_SMC_VLLSCTRL_PORPO) = (v))
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// HW_SMC_PMSTAT - Power Mode Status register
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//-------------------------------------------------------------------------------------------
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#ifndef __LANGUAGE_ASM__
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/*!
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* @brief HW_SMC_PMSTAT - Power Mode Status register (RO)
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*
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* Reset value: 0x01U
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*
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* PMSTAT is a read-only, one-hot register which indicates the current power
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* mode of the system. This register is reset on Chip POR not VLLS and by reset
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* types that trigger Chip POR not VLLS. It is unaffected by reset types that do not
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* trigger Chip POR not VLLS. See the Reset section details for more information.
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*/
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typedef union _hw_smc_pmstat
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{
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uint8_t U;
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struct _hw_smc_pmstat_bitfields
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{
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uint8_t PMSTAT : 7; //!< [6:0]
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uint8_t RESERVED0 : 1; //!< [7]
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} B;
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} hw_smc_pmstat_t;
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#endif
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/*!
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* @name Constants and macros for entire SMC_PMSTAT register
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*/
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//@{
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#define HW_SMC_PMSTAT_ADDR (REGS_SMC_BASE + 0x3U)
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#ifndef __LANGUAGE_ASM__
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#define HW_SMC_PMSTAT (*(__I hw_smc_pmstat_t *) HW_SMC_PMSTAT_ADDR)
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#define HW_SMC_PMSTAT_RD() (HW_SMC_PMSTAT.U)
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#endif
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//@}
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/*
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* Constants & macros for individual SMC_PMSTAT bitfields
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*/
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/*!
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* @name Register SMC_PMSTAT, field PMSTAT[6:0] (RO)
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*
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* When debug is enabled, the PMSTAT will not update to STOP or VLPS
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*/
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//@{
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#define BP_SMC_PMSTAT_PMSTAT (0U) //!< Bit position for SMC_PMSTAT_PMSTAT.
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#define BM_SMC_PMSTAT_PMSTAT (0x7FU) //!< Bit mask for SMC_PMSTAT_PMSTAT.
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#define BS_SMC_PMSTAT_PMSTAT (7U) //!< Bit field size in bits for SMC_PMSTAT_PMSTAT.
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#ifndef __LANGUAGE_ASM__
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//! @brief Read current value of the SMC_PMSTAT_PMSTAT field.
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#define BR_SMC_PMSTAT_PMSTAT (HW_SMC_PMSTAT.B.PMSTAT)
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#endif
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//@}
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//-------------------------------------------------------------------------------------------
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// hw_smc_t - module struct
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//-------------------------------------------------------------------------------------------
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/*!
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* @brief All SMC module registers.
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*/
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#ifndef __LANGUAGE_ASM__
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#pragma pack(1)
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typedef struct _hw_smc
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{
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__IO hw_smc_pmprot_t PMPROT; //!< [0x0] Power Mode Protection register
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__IO hw_smc_pmctrl_t PMCTRL; //!< [0x1] Power Mode Control register
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__IO hw_smc_vllsctrl_t VLLSCTRL; //!< [0x2] VLLS Control register
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__I hw_smc_pmstat_t PMSTAT; //!< [0x3] Power Mode Status register
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} hw_smc_t;
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#pragma pack()
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//! @brief Macro to access all SMC registers.
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//! @return Reference (not a pointer) to the registers struct. To get a pointer to the struct,
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//! use the '&' operator, like <code>&HW_SMC</code>.
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#define HW_SMC (*(hw_smc_t *) REGS_SMC_BASE)
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#endif
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#endif // __HW_SMC_REGISTERS_H__
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// v22/130726/0.9
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// EOF
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