591 lines
22 KiB
C
591 lines
22 KiB
C
/**
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*******************************************************************************
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* @file hc32f4a0_qspi.c
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* @brief This file provides firmware functions to manage the QSPI.
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@verbatim
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Change Logs:
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Date Author Notes
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2020-06-12 Wuze First version
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2020-07-15 Wuze Refined QSPI_WriteData().
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@endverbatim
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*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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*******************************************************************************
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*/
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32f4a0_qspi.h"
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#include "hc32f4a0_utility.h"
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/**
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* @addtogroup HC32F4A0_DDL_Driver
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* @{
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*/
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/**
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* @defgroup DDL_QSPI QSPI
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* @brief QSPI Driver Library
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* @{
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*/
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#if (DDL_QSPI_ENABLE == DDL_ON)
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/*******************************************************************************
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* Local type definitions ('typedef')
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******************************************************************************/
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/*******************************************************************************
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* Local pre-processor symbols/macros ('#define')
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******************************************************************************/
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/**
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* @defgroup QSPI_Local_Macros QSPI Local Macros
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* @{
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*/
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/**
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* @defgroup QSPI_Configuration_Bit_Mask QSPI Configuration Bit Mask
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* @{
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*/
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#define QSPI_FLAG_CLR_MSK (QSPI_FLAG_ROM_ACCESS_ERR)
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_Common_Instruction QSPI Common Instruction
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* @{
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*/
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#define QSPI_INS_ENTER_4BA (0xB7U)
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#define QSPI_INS_EXIT_4BA (0xE9U)
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_Check_Parameters_Validity QSPI check parameters validity
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* @{
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*/
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#define IS_QSPI_CLK_DIV(x) \
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( ((x) >= 2U) && ((x) <= 64U))
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#define IS_QSPI_CS_SETUP_TIMING(x) \
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( ((x) == QSPI_CS_SETUP_BEFORE_0P5_CYCLE) || \
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((x) == QSPI_CS_SETUP_BEFORE_1P5_CYCLE))
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#define IS_QSPI_CS_RELEASE_TIMING(x) \
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( ((x) == QSPI_CS_RELEASE_AFTER_0P5_CYCLE) || \
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((x) == QSPI_CS_RELEASE_AFTER_1P5_CYCLE))
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#define IS_QSPI_CS_IDLE_TIME(x) \
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( ((x) >= 1U) && ((x) <= 16U))
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#define IS_QSPI_CS_EXTEND_TIME(x) \
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( ((x) == QSPI_CS_EXTEND_0CYCLE) || \
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((x) == QSPI_CS_EXTEND_32CYCLE) || \
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((x) == QSPI_CS_EXTEND_128CYCLE) || \
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((x) == QSPI_CS_EXTEND_INFINITE))
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#define IS_QSPI_SPI_MODE(x) \
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( ((x) == QSPI_SPI_MODE_0) || \
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((x) == QSPI_SPI_MODE_3))
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#define IS_QSPI_PREFETCH_STOP_POSITION(x) \
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( ((x) == QSPI_PREFETCH_STOP_BYTE_EDGE) || \
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((x) == QSPI_PREFETCH_STOP_IMMED))
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#define IS_QSPI_READ_MODE(x) \
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( ((x) == QSPI_READ_STANDARD_READ) || \
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((x) == QSPI_READ_FAST_READ) || \
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((x) == QSPI_READ_FAST_READ_DUAL_OUTPUT) || \
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((x) == QSPI_READ_FAST_READ_DUAL_IO) || \
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((x) == QSPI_READ_FAST_READ_QUAD_OUTPUT) || \
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((x) == QSPI_READ_FAST_READ_QUAD_IO) || \
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((x) == QSPI_READ_CUSTOM_STANDARD_READ) || \
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((x) == QSPI_READ_CUSTOM_FAST_READ))
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#define IS_QSPI_COMM_MODE(x) \
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( ((x) == QSPI_COMM_ROM_ACCESS) || \
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((x) == QSPI_COMM_DIRECT_COMM))
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#define IS_QSPI_ADDR_WIDTH(x) \
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( ((x) == QSPI_ADDR_WIDTH_1BYTE) || \
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((x) == QSPI_ADDR_WIDTH_2BYTE) || \
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((x) == QSPI_ADDR_WIDTH_3BYTE) || \
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((x) == QSPI_ADDR_WIDTH_4BYTE))
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#define IS_QSPI_DUMMY_CYCLES(x) \
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( ((x) >= 3U) && ((x) <= 18U))
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#define IS_QSPI_INSTR_MODE(x) \
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( ((x) == QSPI_INSTR_1LINE) || \
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((x) == QSPI_INSTR_2LINE) || \
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((x) == QSPI_INSTR_4LINE))
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#define IS_QSPI_ADDR_MODE(x) \
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( ((x) == QSPI_ADDR_1LINE) || \
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((x) == QSPI_ADDR_2LINE) || \
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((x) == QSPI_ADDR_4LINE))
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#define IS_QSPI_DATA_MODE(x) \
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( ((x) == QSPI_DATA_1LINE) || \
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((x) == QSPI_DATA_2LINE) || \
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((x) == QSPI_DATA_4LINE))
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#define IS_QSPI_BLOCK_NUM(x) \
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( (x) <= 62U)
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#define IS_QSPI_PREFETCH_CMD(x) \
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( ((x) == QSPI_PREFETCH_ENABLE) || \
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((x) == QSPI_PREFETCH_DISABLE))
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#define IS_QSPI_WP_LEVEL(x) \
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( ((x) == QSPI_WP_LOW) || \
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((x) == QSPI_WP_HIGH))
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/**
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* @}
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*/
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/**
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* @defgroup QSPI_Miscellaneous_Macros QSPI Miscellaneous Macros
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* @{
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*/
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#define QSPI_WORD_TO_BYTE(__word__, __au8__) \
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do { \
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(__au8__)[0U] = (uint8_t)(__word__); \
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(__au8__)[1U] = (uint8_t)((__word__) >> 8U); \
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(__au8__)[2U] = (uint8_t)((__word__) >> 16U); \
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(__au8__)[3U] = (uint8_t)((__word__) >> 24U); \
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} while (0U)
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#define QSPI_ROM_MAP_BASE (0x98000000UL)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/*******************************************************************************
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* Global variable definitions (declared in header file with 'extern')
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******************************************************************************/
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/*******************************************************************************
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* Local function prototypes ('static')
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******************************************************************************/
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/*******************************************************************************
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* Local variable definitions ('static')
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******************************************************************************/
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/*******************************************************************************
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* Function implementation - global ('extern') and local ('static')
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******************************************************************************/
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/**
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* @defgroup QSPI_Global_Functions QSPI Global Functions
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* @{
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*/
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/**
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* @brief Initializes QSPI peripheral according to the specified parameters \
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* in the structure stc_qspi_init_t
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* @param [in] pstcInit Pointer to a stc_qspi_init_t structure value that \
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* contains the configuration information for QSPI.
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* @retval An en_result_t enumeration type value.
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* @arg Ok: No error occurred.
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* @arg ErrorInvalidParameter: pstcInit == NULL.
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*/
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en_result_t QSPI_Init(const stc_qspi_init_t *pstcInit)
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{
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uint32_t u32DutyCorrection = 0U;
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en_result_t enRet = ErrorInvalidParameter;
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if (pstcInit != NULL)
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{
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DDL_ASSERT(IS_QSPI_CLK_DIV(pstcInit->u32ClkDiv));
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DDL_ASSERT(IS_QSPI_CS_SETUP_TIMING(pstcInit->u32CSSetupTiming));
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DDL_ASSERT(IS_QSPI_CS_RELEASE_TIMING(pstcInit->u32CSReleaseTiming));
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DDL_ASSERT(IS_QSPI_CS_IDLE_TIME(pstcInit->u32CSIdleTime));
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DDL_ASSERT(IS_QSPI_CS_EXTEND_TIME(pstcInit->u32CSExtendTime));
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DDL_ASSERT(IS_QSPI_SPI_MODE(pstcInit->u32SPIMode));
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DDL_ASSERT(IS_QSPI_PREFETCH_STOP_POSITION(pstcInit->u32PrefetchStopPos));
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DDL_ASSERT(IS_QSPI_PREFETCH_CMD(pstcInit->u32PrefetchCmd));
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DDL_ASSERT(IS_QSPI_WP_LEVEL(pstcInit->u32WPLevel));
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DDL_ASSERT(IS_QSPI_READ_MODE(pstcInit->u32ReadMode));
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DDL_ASSERT(IS_QSPI_COMM_MODE(pstcInit->u32CommMode));
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DDL_ASSERT(IS_QSPI_ADDR_WIDTH(pstcInit->u32AddrWidth));
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DDL_ASSERT(IS_QSPI_DUMMY_CYCLES(pstcInit->u32DummyCycles));
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DDL_ASSERT(IS_QSPI_INSTR_MODE(pstcInit->u32InstrMode));
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DDL_ASSERT(IS_QSPI_ADDR_MODE(pstcInit->u32AddrMode));
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DDL_ASSERT(IS_QSPI_DATA_MODE(pstcInit->u32DataMode));
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if ((pstcInit->u32ClkDiv & 1UL) != 0UL)
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{
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u32DutyCorrection = QSPI_FCR_DUTY;
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}
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WRITE_REG32(M4_QSPI->CR, (((pstcInit->u32ClkDiv-1UL) << QSPI_CR_DIV_POS) | \
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pstcInit->u32SPIMode | \
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pstcInit->u32PrefetchStopPos | \
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pstcInit->u32PrefetchCmd | \
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pstcInit->u32ReadMode | \
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pstcInit->u32CommMode | \
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pstcInit->u32InstrMode | \
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pstcInit->u32AddrMode | \
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pstcInit->u32DataMode));
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WRITE_REG32(M4_QSPI->CSCR, (pstcInit->u32CSExtendTime | \
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(pstcInit->u32CSIdleTime-1UL)));
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WRITE_REG32(M4_QSPI->FCR, (pstcInit->u32CSSetupTiming | \
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pstcInit->u32CSReleaseTiming | \
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pstcInit->u32AddrWidth | \
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((pstcInit->u32DummyCycles-3UL) << QSPI_FCR_DMCYCN_POS) | \
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pstcInit->u32WPLevel | \
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u32DutyCorrection));
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WRITE_REG32(M4_QSPI->CCMD, pstcInit->u8RomAccessInstr);
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enRet = Ok;
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}
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return enRet;
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}
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/**
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* @brief De-initializes QSPI peripheral. Reset the registers of QSPI.
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* @param None
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* @retval None
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*/
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void QSPI_DeInit(void)
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{
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WRITE_REG32(M4_QSPI->CR, 0x3F0000UL);
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WRITE_REG32(M4_QSPI->CSCR, 0xFUL);
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WRITE_REG32(M4_QSPI->FCR, 0x80B3UL);
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WRITE_REG32(M4_QSPI->SR, 0x8000UL);
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WRITE_REG32(M4_QSPI->CCMD, 0x0UL);
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WRITE_REG32(M4_QSPI->XCMD, 0xFFUL);
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WRITE_REG32(M4_QSPI->SR2, QSPI_FLAG_ROM_ACCESS_ERR);
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WRITE_REG32(M4_QSPI->EXAR, 0x0UL);
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}
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/**
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* @brief Set a default value for QSPI initialization structure.
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* @param [in] pstcInit Pointer to a stc_qspi_init_t structure value that \
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* contains the configuration information QSPI.
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* @retval An en_result_t enumeration type value.
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* @arg Ok: No error occurred.
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* @arg ErrorInvalidParameter: pstcInit == NULL.
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*/
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en_result_t QSPI_StructInit(stc_qspi_init_t *pstcInit)
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{
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en_result_t enRet = ErrorInvalidParameter;
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if (pstcInit != NULL)
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{
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pstcInit->u32ClkDiv = 2UL;
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pstcInit->u32CSSetupTiming = QSPI_CS_SETUP_BEFORE_0P5_CYCLE;
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pstcInit->u32CSReleaseTiming = QSPI_CS_RELEASE_AFTER_0P5_CYCLE;
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pstcInit->u32CSIdleTime = 1UL;
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pstcInit->u32CSExtendTime = QSPI_CS_EXTEND_0CYCLE;
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pstcInit->u32SPIMode = QSPI_SPI_MODE_0;
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pstcInit->u32PrefetchStopPos = QSPI_PREFETCH_STOP_BYTE_EDGE;
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pstcInit->u32PrefetchCmd = QSPI_PREFETCH_ENABLE;
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pstcInit->u32WPLevel = QSPI_WP_HIGH;
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pstcInit->u32CommMode = QSPI_COMM_ROM_ACCESS;
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pstcInit->u32AddrWidth = QSPI_ADDR_WIDTH_3BYTE;
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pstcInit->u32InstrMode = QSPI_INSTR_1LINE;
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pstcInit->u32AddrMode = QSPI_ADDR_1LINE;
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pstcInit->u32DataMode = QSPI_DATA_1LINE;
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pstcInit->u32ReadMode = QSPI_READ_STANDARD_READ;
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pstcInit->u8RomAccessInstr = 0x0U;
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pstcInit->u32DummyCycles = 3UL;
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enRet = Ok;
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}
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return enRet;
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}
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/**
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* @brief QSPI write data.
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* @param [in] u32Instr Instruction.
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* @param [in] u32Address Address.
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* @param [in] pu8Src Pointer to an array that stores the data to be written.
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* @param [in] u32SrcSize Size of the data to be written.
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* @retval An en_result_t enumeration type value.
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* @arg Ok: No error occurred.
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* @arg ErrorInvalidParameter: pu8Src == NULL or u32SrcSize == 0U
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*/
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en_result_t QSPI_WriteData(uint32_t u32Instr, uint32_t u32Address, \
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const uint8_t pu8Src[], uint32_t u32SrcSize)
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{
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uint32_t i;
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uint8_t au8Address[4U];
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uint32_t u32AddrWidth;
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en_result_t enRet = ErrorInvalidParameter;
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if ((pu8Src != NULL) && (u32SrcSize > 0U))
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{
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QSPI_WORD_TO_BYTE(u32Address, au8Address);
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u32AddrWidth = (READ_REG32_BIT(M4_QSPI->FCR, QSPI_FCR_AWSL) >> QSPI_FCR_AWSL_POS) + 1U;
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/* Enter direct communication mode. */
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QSPI_EnterDirectCommMode();
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/* Send instruction. */
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WRITE_REG32(M4_QSPI->DCOM, u32Instr);
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/* Send ROM address. */
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for (i=0U; i<u32AddrWidth; i++)
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{
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WRITE_REG32(M4_QSPI->DCOM, au8Address[i]);
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}
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/* Write data at last. */
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for (i=0U; i<u32SrcSize; i++)
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{
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WRITE_REG32(M4_QSPI->DCOM, pu8Src[i]);
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}
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/* Exit direct communication mode. */
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QSPI_ExitDirectCommMode();
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enRet = Ok;
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}
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return enRet;
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}
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/**
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* @brief QSPI write data.
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* @param [in] u32Address Address.
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* @param [in] pu8Dest Pointer to an array that used to store the read data.
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* @param [in] u32DestSize Size of the data to be read.
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* @retval An en_result_t enumeration type value.
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* @arg Ok: No error occurred.
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* @arg ErrorInvalidParameter: pu8Dest == NULL or u32DestSize == 0U
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*/
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en_result_t QSPI_ReadData(uint32_t u32Address, uint8_t pu8Dest[], uint32_t u32DestSize)
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{
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uint32_t i = 0U;
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en_result_t enRet = ErrorInvalidParameter;
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if ((pu8Dest != NULL) && (u32DestSize > 0U))
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{
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u32Address += QSPI_ROM_MAP_BASE;
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while (u32DestSize-- != 0U)
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{
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pu8Dest[i++] = *(uint8_t *)(u32Address++);
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}
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enRet = Ok;
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}
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return enRet;
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}
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/**
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* @brief Specifies read mode.
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* @param [in] u32ReadMode QSPI read mode.
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* This parameter can be a value of @ref QSPI_Read_Mode
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* @arg QSPI_READ_STANDARD_READ: Standard read mode (no dummy cycles).
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* @arg QSPI_READ_FAST_READ: Fast read mode (dummy cycles between address and data).
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* @arg QSPI_READ_FAST_READ_DUAL_OUTPUT: Fast read dual output mode (data on 2 lines).
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* @arg QSPI_READ_FAST_READ_DUAL_IO: Fast read dual I/O mode (address and data on 2 lines).
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* @arg QSPI_READ_FAST_READ_QUAD_OUTPUT: Fast read quad output mode (data on 4 lines).
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* @arg QSPI_READ_FAST_READ_QUAD_IO: Fast read quad I/O mode (address and data on 4 lines).
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* @arg QSPI_READ_CUSTOM_STANDARD_READ: Custom standard read mode.
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* @arg QSPI_READ_CUSTOM_FAST_READ: Custom fast read mode.
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* @param [in] u8ReadInstr Read instruction of QSPI flash. Tis instruction must correspond to the read mode that specified by parameter 'u32ReadMode'.
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* @param [in] u32DummyCycles The number of dummy cycles for fast read. It must correspond to the QSPI flash read instruction.
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* Ignore when u32ReadMode == QSPI_READ_STANDARD_READ.
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* This parameter can be a value between 3U and 18U, inclusive.
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* @retval None
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*/
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void QSPI_SetReadMode(uint32_t u32ReadMode, uint8_t u8ReadInstr, uint32_t u32DummyCycles)
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{
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DDL_ASSERT(IS_QSPI_READ_MODE(u32ReadMode));
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DDL_ASSERT(IS_QSPI_DUMMY_CYCLES(u32DummyCycles));
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MODIFY_REG32(M4_QSPI->FCR, QSPI_FCR_DMCYCN, (u32DummyCycles-3UL) << QSPI_FCR_DMCYCN_POS);
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MODIFY_REG32(M4_QSPI->CR, QSPI_CR_MDSEL, u32ReadMode);
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WRITE_REG32(M4_QSPI->CCMD, u8ReadInstr);
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}
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/**
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* @brief Enable or disable duty correction.
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* @param [in] enNewState An en_functional_state_t enumeration type value.
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* @arg Enable: Enable duty correction.
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* @arg Disable: Disable duty correction.
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* @retval None
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*/
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void QSPI_DutyCorrectCmd(en_functional_state_t enNewState)
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{
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DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
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if (enNewState == Enable)
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{
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SET_REG32_BIT(M4_QSPI->FCR, QSPI_FCR_DUTY);
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}
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else
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{
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CLEAR_REG32_BIT(M4_QSPI->FCR, QSPI_FCR_DUTY);
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}
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}
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/**
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* @brief Enable or disable prefetch function.
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* @param [in] enNewState An en_functional_state_t enumeration type value.
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* @arg Enable: Enable prefetch function.
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* @arg Disable: Disable prefetch function.
|
|
* @retval None
|
|
*/
|
|
void QSPI_PrefetchCmd(en_functional_state_t enNewState)
|
|
{
|
|
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
|
if (enNewState == Enable)
|
|
{
|
|
SET_REG32_BIT(M4_QSPI->CR, QSPI_CR_PFE);
|
|
}
|
|
else
|
|
{
|
|
CLEAR_REG32_BIT(M4_QSPI->CR, QSPI_CR_PFE);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Enable or disable XIP mode.
|
|
* @param [in] enNewState An en_functional_state_t enumeration type value.
|
|
* @arg Enable: Enable XIP mode.
|
|
* @arg Disable: Disable XIP mode.
|
|
* @retval None
|
|
*/
|
|
void QSPI_XIPModeCmd(en_functional_state_t enNewState)
|
|
{
|
|
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
|
if (enNewState == Enable)
|
|
{
|
|
SET_REG32_BIT(M4_QSPI->CR, QSPI_CR_XIPE);
|
|
}
|
|
else
|
|
{
|
|
CLEAR_REG32_BIT(M4_QSPI->CR, QSPI_CR_XIPE);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Specifies the level of WP.
|
|
* @param [in] u32Level The level of WP.
|
|
* This parameter can be a value of @ref QSPI_WP_Level
|
|
* @arg QSPI_WP_LOW: Set WP output low.
|
|
* @arg QSPI_WP_HIGH: Set WP output high.
|
|
* @retval None
|
|
*/
|
|
void QSPI_SetWPPinLevel(uint32_t u32Level)
|
|
{
|
|
DDL_ASSERT(IS_QSPI_WP_LEVEL(u32Level));
|
|
MODIFY_REG32(M4_QSPI->FCR, QSPI_FCR_WPOL, u32Level);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable or disable 4-byte address mode.
|
|
* @param [in] enNewState An en_functional_state_t enumeration type value.
|
|
* @arg Enable: Enable 4-byte address mode.
|
|
* @arg Disable: Disable 4-byte address mode.
|
|
* @retval None
|
|
*/
|
|
void QSPI_4ByteAddrModeCmd(en_functional_state_t enNewState)
|
|
{
|
|
DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState));
|
|
if (enNewState == Enable)
|
|
{
|
|
SET_REG32_BIT(M4_QSPI->FCR, QSPI_FCR_FOUR_BIC);
|
|
}
|
|
else
|
|
{
|
|
CLEAR_REG32_BIT(M4_QSPI->FCR, QSPI_FCR_FOUR_BIC);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Selects the block to access.
|
|
* @param [in] u32Block External block. A number between 0U and 62U, inclusive.
|
|
* @retval None
|
|
*/
|
|
void QSPI_SelectBlock(uint32_t u32Block)
|
|
{
|
|
DDL_ASSERT(IS_QSPI_BLOCK_NUM(u32Block));
|
|
WRITE_REG32(M4_QSPI->EXAR, ((u32Block << QSPI_EXAR_EXADR_POS) & QSPI_EXAR_EXADR));
|
|
}
|
|
|
|
/**
|
|
* @brief Get the size of prefetched data.
|
|
* @param None
|
|
* @retval A number between 0U and 18U, inclusive.
|
|
*/
|
|
uint32_t QSPI_GetPrefetchedSize(void)
|
|
{
|
|
return READ_REG32_BIT(M4_QSPI->SR, QSPI_SR_PFNUM) >> QSPI_SR_PFNUM_POS;
|
|
}
|
|
|
|
/**
|
|
* @brief Get the status of the specified QSPI flags.
|
|
* @param [in] u32Flag The status flags of QSPI.
|
|
* This parameter can be values of @ref QSPI_Status_Flag
|
|
* @arg QSPI_FLAG_DIRECT_COMM_BUSY: Serial transfer being processed.
|
|
* @arg QSPI_FLAG_XIP_MODE: XIP mode.
|
|
* @arg QSPI_FLAG_ROM_ACCESS_ERR: ROM access detection status in direct communication mode.
|
|
* @arg QSPI_FLAG_PREFETCH_BUF_FULL: Prefetch buffer is full.
|
|
* @arg QSPI_FLAG_PREFETCH_ACTIVE: Prefetch function operating.
|
|
* @retval An en_flag_status_t enumeration type value.
|
|
* @arg Set: At least one of the specified flags is set.
|
|
* @arg Reset: None of the specified flags is set.
|
|
*/
|
|
en_flag_status_t QSPI_GetStatus(uint32_t u32Flag)
|
|
{
|
|
en_flag_status_t enFlag = Reset;
|
|
|
|
if (READ_REG32_BIT(M4_QSPI->SR, (u32Flag & QSPI_FLAG_ALL)) != 0UL)
|
|
{
|
|
enFlag = Set;
|
|
}
|
|
|
|
return enFlag;
|
|
}
|
|
|
|
/**
|
|
* @brief Clear the specified flag.
|
|
* @param [in] u32Flag The specified flags to be cleared.
|
|
* This parameter can only be the following:
|
|
* @arg QSPI_FLAG_ROM_ACCESS_ERR: ROM access detection status in direct communication mode.
|
|
* @retval None
|
|
*/
|
|
void QSPI_ClrStatus(uint32_t u32Flag)
|
|
{
|
|
SET_REG32_BIT(M4_QSPI->SR2, (u32Flag & QSPI_FLAG_CLR_MSK));
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* DDL_QSPI_ENABLE */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/******************************************************************************
|
|
* EOF (not truncated)
|
|
*****************************************************************************/
|