257 lines
7.1 KiB
C
257 lines
7.1 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety first version
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*/
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#include <rtthread.h>
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#include "at91sam9g45.h"
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static rt_list_t clocks;
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struct clk {
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char name[32];
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rt_uint32_t rate_hz;
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struct clk *parent;
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rt_list_t node;
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};
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static struct clk clk32k = {
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"clk32k",
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AT91C_SLOW_CLOCK,
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RT_NULL,
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{RT_NULL, RT_NULL},
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};
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static struct clk main_clk = {
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"main",
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0,
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RT_NULL,
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{RT_NULL, RT_NULL},
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};
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static struct clk plla = {
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"plla",
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0,
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&main_clk,
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{RT_NULL, RT_NULL},
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};
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static struct clk mck = {
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"mck",
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0,
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RT_NULL,
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{RT_NULL, RT_NULL},
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};
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static struct clk upllck = {
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"upllck",
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480*1000*1000,
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&main_clk,
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{RT_NULL, RT_NULL},
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};
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static struct clk *const standard_pmc_clocks[] = {
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/* four primary clocks */
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&clk32k,
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&main_clk,
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&plla,
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/* MCK */
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&mck
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};
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/* clocks cannot be de-registered no refcounting necessary */
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struct clk *clk_get(const char *id)
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{
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struct clk *clk;
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rt_list_t *list;
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for (list = (&clocks)->next; list != &clocks; list = list->next)
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{
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clk = (struct clk *)rt_list_entry(list, struct clk, node);
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if (rt_strcmp(id, clk->name) == 0)
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return clk;
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}
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return RT_NULL;
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}
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rt_uint32_t clk_get_rate(struct clk *clk)
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{
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rt_uint32_t rate;
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for (;;) {
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rate = clk->rate_hz;
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if (rate || !clk->parent)
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break;
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clk = clk->parent;
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}
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return rate;
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}
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static void at91_upllck_init(rt_uint32_t main_clock)
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{
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// EHCI USB use fixed 480MHz clock
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}
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static struct clk *at91_css_to_clk(unsigned long css)
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{
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switch (css) {
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case AT91C_PMC_CSS_SLOW_CLK:
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return &clk32k;
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case AT91C_PMC_CSS_MAIN_CLK:
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return &main_clk;
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case AT91C_PMC_CSS_PLLA_CLK:
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return &plla;
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case AT91C_PMC_CSS_UPLL_CLK:
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return &upllck;
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}
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return RT_NULL;
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}
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// TODO: how to auto-set register value by OSC and MCK
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/* Settings at 400/133MHz */
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// In datasheet, ATMEL says 12MHz main crystal startup time less than 2ms, so we
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// configure OSC startup timeout to 64*8/32768=15.6ms, should enough
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#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8))
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// MAINCK => Divider(DIVA) => PLLA(MULA, OUTA) => /1/2 Divider(PLLADIV2) => PLLACK
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// pls. refer to doc6438G figure 24-6 on pg294. ICPLLA in reg PMC_PLLICPR
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// 12MHz / 3 * (199 + 1) = 800MHz
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// OUTA/ICPLLA can as ICPLLA:OUTA[1]:OUTA[0] = (800-PLLAOUT(MHz))/50
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// PLLACOUNT field occupy bit[13:8], max value is 0x3F, then about 19.2ms
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#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_0)
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#define BOARD_PLLACOUNT (0x3F << 8)
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#define BOARD_MULA (AT91C_CKGR_MULA & (199 << 16))
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#define BOARD_DIVA (AT91C_CKGR_DIVA & 3)
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// Clock Source => select(CCS) => Prescaler(PRES) => Master Clock Divider(MDIV) => MCK
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// => Processor Clock Divider => PCK
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// Master clock can refer to doc6438G figure 25-2 on pg298
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// PLLADIV2=1(div 2, 400MHz), PRES=0(no div, 400MHz),
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// MDIV=3(Master Clock divided by 3, 133MHz), CSS=0(still Slow Clock)
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#define BOARD_PRESCALER (0x00001300) //400/133MHz
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#define MHz(n) ((n) * 1000 * 1000)
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#define OSC_FREQ MHz(12)
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#define PLLA_FREQ MHz(800)
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static void at91_plla_init(void)
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{
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rt_uint32_t pllar, mckr;
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// Code refer to doc6438G, 25.10 Programming Sequence
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/* Initialize main oscillator
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****************************/
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// enable main OSC and wait OSC startup time timeout.
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AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN;
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
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/* Initialize PLLA, Set PLL to 800MHz and wait PLL stable */
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pllar = (MHz(800) - PLLA_FREQ) / MHz(50); // please refer to Table 46-15 of doc 6438G
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AT91C_BASE_PMC->PMC_PLLICPR = (pllar >> 2) & 1; // ICPLLA
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pllar = (pllar & 3) << 14; // OUTA
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pllar |= BOARD_DIVA; // PLLA input clock as 4MHz
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pllar |= BOARD_MULA; // PLLA output clock as 800MHz
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pllar |= BOARD_PLLACOUNT;
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pllar |= AT91C_CKGR_SRCA; // I don't known what means, but seems must set it
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AT91C_BASE_PMC->PMC_PLLAR = pllar;
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));
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/* Wait for the master clock if it was already initialized */
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// make sure Master clock in READY status before operate it
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
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/* Switch to fast clock
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**********************/
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/* setup main clock divisor and prescaler, 400MHz/133MHz, but don't switch */
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mckr = AT91C_BASE_PMC->PMC_MCKR;
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if ((mckr & AT91C_PMC_MDIV) != (BOARD_PRESCALER & AT91C_PMC_MDIV))
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{
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mckr = (mckr & ~(unsigned int)AT91C_PMC_MDIV) | (BOARD_PRESCALER & AT91C_PMC_MDIV);
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AT91C_BASE_PMC->PMC_MCKR = mckr;
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
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}
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/* Switch to PLL + prescaler, now Switch to PLLA as source, run on the fly */
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if ((mckr & AT91C_PMC_CSS) != AT91C_PMC_CSS_PLLA_CLK)
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{
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mckr = (mckr & ~(unsigned int)AT91C_PMC_CSS) | AT91C_PMC_CSS_PLLA_CLK;
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AT91C_BASE_PMC->PMC_MCKR = mckr;
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
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}
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plla.rate_hz = PLLA_FREQ;
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}
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#define false 0
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#define true 1
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int at91_clock_init(rt_uint32_t main_clock)
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{
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unsigned tmp, freq, mckr, mdiv;
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int i;
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/*
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* When the bootloader initialized the main oscillator correctly,
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* there's no problem using the cycle counter. But if it didn't,
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* or when using oscillator bypass mode, we must be told the speed
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* of the main clock.
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*/
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if (!main_clock) {
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do {
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tmp = readl(AT91C_CKGR_MCFR);
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} while (!(tmp & AT91C_CKGR_MAINRDY));
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main_clock = (tmp & AT91C_CKGR_MAINF) * (AT91C_SLOW_CLOCK / 16);
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}
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main_clk.rate_hz = main_clock;
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at91_plla_init();
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at91_upllck_init(main_clock);
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/*
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* MCK and CPU derive from one of those primary clocks.
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* For now, assume this parentage won't change.
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*/
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mckr = readl(AT91C_PMC_MCKR);
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mck.parent = at91_css_to_clk(mckr & AT91C_PMC_CSS);
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freq = mck.parent->rate_hz;
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freq /= (1 << ((mckr & AT91C_PMC_PRES) >> 2)); /* prescale */
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mdiv = 1 << ((mckr & AT91C_PMC_MDIV) >> 8);
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if (mdiv == 8) mdiv = 3;
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freq /= mdiv; /* mdiv */
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if (mckr & AT91C_PMC_PLLADIV2) freq /= 2; /* plla_div2 */
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mck.rate_hz = freq;
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/* Register the PMC's standard clocks */
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rt_list_init(&clocks);
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for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
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rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
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rt_list_insert_after(&clocks, &upllck.node);
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/* MCK and CPU clock are "always on" */
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//clk_enable(&mck);
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/*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
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freq / 1000000, (unsigned) mck.rate_hz / 1000000,
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(unsigned) main_clock / 1000000,
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((unsigned) main_clock % 1000000) / 1000);*///cause blocked
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return 0;
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}
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/**
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* @brief System Clock Configuration
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*/
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void rt_hw_clock_init(void)
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{
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at91_clock_init(MHz(12));
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}
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