212 lines
4.9 KiB
C
212 lines
4.9 KiB
C
/*""FILE COMMENT""*******************************************************
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* System Name : Timer TMR API for RX62Nxx
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* File Name : r_pdl_tmr.h
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* Version : 1.02
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* Contents : Timer TMR API header
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* Customer :
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* Model :
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* Order :
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* CPU : RX
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* Compiler : RXC
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* OS : Nothing
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* Programmer :
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* Note :
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************************************************************************
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* Copyright, 2011. Renesas Electronics Corporation
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* and Renesas Solutions Corporation
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************************************************************************
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* History : 2011.04.08
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* : Ver 1.02
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* : CS-5 release.
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*""FILE COMMENT END""**************************************************/
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#ifndef R_PDL_TMR_H
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#define R_PDL_TMR_H
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#include "r_pdl_common_defs_RX62Nxx.h"
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/* Function prototypes */
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bool R_TMR_Set(
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uint8_t
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);
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bool R_TMR_CreateChannel(
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uint8_t,
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uint32_t,
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uint8_t,
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uint8_t,
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uint8_t,
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uint8_t,
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void *,
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void *,
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void *,
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uint8_t
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);
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bool R_TMR_CreateUnit(
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uint8_t,
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uint32_t,
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uint8_t,
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uint16_t,
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uint16_t,
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uint16_t,
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void *,
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void *,
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void *,
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uint8_t
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);
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bool R_TMR_CreatePeriodic(
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uint8_t,
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uint32_t,
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float,
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float,
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void *,
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void *,
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uint8_t
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);
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bool R_TMR_CreateOneShot(
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uint8_t,
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uint32_t,
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float,
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void *,
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uint8_t
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);
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bool R_TMR_Destroy(
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uint8_t
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);
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bool R_TMR_ControlChannel(
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uint8_t,
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uint32_t,
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uint8_t,
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uint8_t,
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uint8_t
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);
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bool R_TMR_ControlUnit(
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uint8_t,
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uint32_t,
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uint16_t,
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uint16_t,
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uint16_t
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);
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bool R_TMR_ControlPeriodic(
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uint8_t,
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uint32_t,
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float,
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float
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);
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bool R_TMR_ReadChannel(
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uint8_t,
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uint8_t *,
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uint8_t *,
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uint8_t *,
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uint8_t *
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);
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bool R_TMR_ReadUnit(
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uint8_t,
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uint8_t *,
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uint16_t *,
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uint16_t *,
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uint16_t *
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);
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/* Pin selection */
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#define PDL_TMR_PIN_TMR0_A 0x01u
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#define PDL_TMR_PIN_TMR0_B 0x02u
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#define PDL_TMR_PIN_TMR1_A 0x04u
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#define PDL_TMR_PIN_TMR1_B 0x08u
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#define PDL_TMR_PIN_TMR2_A 0x10u
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#define PDL_TMR_PIN_TMR2_B 0x20u
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#define PDL_TMR_PIN_TMR3_A 0x40u
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#define PDL_TMR_PIN_TMR3_B 0x80u
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/* Counter clock sources */
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#define PDL_TMR_CLK_OFF 0x00000001ul
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#define PDL_TMR_CLK_EXT_RISING 0x00000002ul
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#define PDL_TMR_CLK_EXT_FALLING 0x00000004ul
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#define PDL_TMR_CLK_EXT_BOTH 0x00000008ul
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#define PDL_TMR_CLK_PCLK_DIV_1 0x00000010ul
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#define PDL_TMR_CLK_PCLK_DIV_2 0x00000020ul
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#define PDL_TMR_CLK_PCLK_DIV_8 0x00000040ul
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#define PDL_TMR_CLK_PCLK_DIV_32 0x00000080ul
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#define PDL_TMR_CLK_PCLK_DIV_64 0x00000100ul
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#define PDL_TMR_CLK_PCLK_DIV_1024 0x00000200ul
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#define PDL_TMR_CLK_PCLK_DIV_8192 0x00000400ul
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#define PDL_TMR_CLK_TMR1_OVERFLOW 0x00000800ul
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#define PDL_TMR_CLK_TMR3_OVERFLOW 0x00001000ul
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#define PDL_TMR_CLK_TMR0_CM_A 0x00002000ul
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#define PDL_TMR_CLK_TMR2_CM_A 0x00004000ul
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/* A/D trigger control */
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#define PDL_TMR_ADC_TRIGGER_DISABLE 0x00008000ul
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#define PDL_TMR_ADC_TRIGGER_ENABLE 0x00010000ul
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/* Counter clearing options */
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#define PDL_TMR_CLEAR_DISABLE 0x00020000ul
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#define PDL_TMR_CLEAR_CM_A 0x00040000ul
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#define PDL_TMR_CLEAR_CM_B 0x00080000ul
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#define PDL_TMR_CLEAR_RESET_RISING 0x00100000ul
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#define PDL_TMR_CLEAR_RESET_HIGH 0x00200000ul
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/* DTC CMA trigger control */
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#define PDL_TMR_CM_A_DTC_TRIGGER_DISABLE 0x00400000ul
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#define PDL_TMR_CM_A_DTC_TRIGGER_ENABLE 0x00800000ul
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/* DTC CMB trigger control */
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#define PDL_TMR_CM_B_DTC_TRIGGER_DISABLE 0x01000000ul
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#define PDL_TMR_CM_B_DTC_TRIGGER_ENABLE 0x02000000ul
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/* Output control options */
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#define PDL_TMR_OUTPUT_IGNORE_CM_A 0x01u
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#define PDL_TMR_OUTPUT_LOW_CM_A 0x02u
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#define PDL_TMR_OUTPUT_HIGH_CM_A 0x04u
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#define PDL_TMR_OUTPUT_INV_CM_A 0x08u
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#define PDL_TMR_OUTPUT_IGNORE_CM_B 0x10u
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#define PDL_TMR_OUTPUT_LOW_CM_B 0x20u
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#define PDL_TMR_OUTPUT_HIGH_CM_B 0x40u
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#define PDL_TMR_OUTPUT_INV_CM_B 0x80u
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/* Channels and units */
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#define PDL_TMR_TMR0 0
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#define PDL_TMR_TMR1 1
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#define PDL_TMR_TMR2 2
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#define PDL_TMR_TMR3 3
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#define PDL_TMR_UNIT0 4
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#define PDL_TMR_UNIT1 5
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/* Period or frequency selection */
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#define PDL_TMR_PERIOD 0x00000001ul
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#define PDL_TMR_FREQUENCY 0x00000002ul
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/* Output pin control */
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#define PDL_TMR_OUTPUT_HIGH 0x00000004ul
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#define PDL_TMR_OUTPUT_LOW 0x00000008ul
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#define PDL_TMR_OUTPUT_OFF 0x00000010ul
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#define PDL_TMR_OUTPUT_ENABLE 0x00000020ul
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#define PDL_TMR_OUTPUT_DISABLE 0x00000040ul
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/* ADC trigger control */
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#define PDL_TMR_ADC_TRIGGER_ON 0x00000080ul
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#define PDL_TMR_ADC_TRIGGER_OFF 0x00000100ul
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/* Pulse DTC trigger control */
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#define PDL_TMR_PULSE_DTC_TRIGGER_DISABLE 0x00000200ul
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#define PDL_TMR_PULSE_DTC_TRIGGER_ENABLE 0x00000400ul
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/* Period DTC trigger control */
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#define PDL_TMR_PERIOD_DTC_TRIGGER_DISABLE 0x00000800ul
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#define PDL_TMR_PERIOD_DTC_TRIGGER_ENABLE 0x00001000ul
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/* CPU control */
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#define PDL_TMR_CPU_ON 0x00002000ul
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#define PDL_TMR_CPU_OFF 0x00004000ul
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/* Timer counter control */
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#define PDL_TMR_STOP 0x00008000ul
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#define PDL_TMR_START 0x00010000ul
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/* Register selections */
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#define PDL_TMR_COUNTER 0x00020000ul
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#define PDL_TMR_TIME_CONSTANT_A 0x00040000ul
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#define PDL_TMR_TIME_CONSTANT_B 0x00080000ul
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#endif
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/* End of file */
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