387 lines
10 KiB
C
387 lines
10 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-20 Bernard first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include <board.h>
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#include <armv8.h>
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#include "interrupt.h"
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#include "mm_aspace.h"
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#define DBG_TAG "libcpu.trap"
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#define DBG_LVL DBG_LOG
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#include <rtdbg.h>
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#ifdef RT_USING_FINSH
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extern long list_thread(void);
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#endif
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#ifdef RT_USING_LWP
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#include <lwp.h>
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#include <lwp_arch.h>
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#ifdef LWP_USING_CORE_DUMP
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#include <lwp_core_dump.h>
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#endif
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static void _check_fault(struct rt_hw_exp_stack *regs, uint32_t pc_adj, char *info)
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{
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uint32_t is_user_fault;
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rt_thread_t th;
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is_user_fault = !(regs->cpsr & 0x1f);
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if (is_user_fault)
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{
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rt_kprintf("%s! pc = 0x%x\n", info, regs->pc - pc_adj);
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}
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/* user stack backtrace */
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th = rt_thread_self();
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if (th && th->lwp)
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{
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arch_backtrace_uthread(th);
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}
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if (is_user_fault)
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{
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#ifdef LWP_USING_CORE_DUMP
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lwp_core_dump(regs, pc_adj);
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#endif
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sys_exit_group(-1);
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}
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}
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rt_inline int _get_type(unsigned long esr)
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{
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int ret;
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int fsc = ARM64_ESR_EXTRACT_FSC(esr);
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switch (fsc)
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{
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case ARM64_FSC_TRANSLATION_FAULT_LEVEL_0:
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case ARM64_FSC_TRANSLATION_FAULT_LEVEL_1:
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case ARM64_FSC_TRANSLATION_FAULT_LEVEL_2:
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case ARM64_FSC_TRANSLATION_FAULT_LEVEL_3:
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ret = MM_FAULT_TYPE_PAGE_FAULT;
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break;
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case ARM64_FSC_PERMISSION_FAULT_LEVEL_0:
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case ARM64_FSC_PERMISSION_FAULT_LEVEL_1:
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case ARM64_FSC_PERMISSION_FAULT_LEVEL_2:
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case ARM64_FSC_PERMISSION_FAULT_LEVEL_3:
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ret = MM_FAULT_TYPE_RWX_PERM;
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break;
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case ARM64_FSC_ACCESS_FLAG_FAULT_LEVEL_0:
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case ARM64_FSC_ACCESS_FLAG_FAULT_LEVEL_1:
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case ARM64_FSC_ACCESS_FLAG_FAULT_LEVEL_2:
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case ARM64_FSC_ACCESS_FLAG_FAULT_LEVEL_3:
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/* access flag fault, not handle currently */
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default:
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ret = MM_FAULT_TYPE_GENERIC;
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}
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return ret;
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}
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rt_inline long _irq_is_disable(long cpsr)
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{
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return !!(cpsr & 0x80);
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}
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static int user_fault_fixable(unsigned long esr, struct rt_hw_exp_stack *regs)
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{
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rt_ubase_t level;
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enum rt_mm_fault_op fault_op;
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enum rt_mm_fault_type fault_type;
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struct rt_lwp *lwp;
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void *dfar;
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int ret = 0;
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unsigned char ec = ARM64_ESR_EXTRACT_EC(esr);
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rt_bool_t is_write = ARM64_ABORT_WNR(esr);
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switch (ec)
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{
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case ARM64_EC_INST_ABORT_FROM_LO_EXCEPTION:
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fault_op = MM_FAULT_OP_EXECUTE;
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fault_type = _get_type(esr);
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break;
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case ARM64_EC_INST_ABORT_WITHOUT_A_CHANGE:
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case ARM64_EC_DATA_ABORT_FROM_LO_EXCEPTION:
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case ARM64_EC_DATA_ABORT_WITHOUT_A_CHANGE:
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fault_op = is_write ? MM_FAULT_OP_WRITE : MM_FAULT_OP_READ;
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fault_type = _get_type(esr);
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break;
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default:
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/* non-fixable */
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fault_op = 0;
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break;
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}
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/* page fault exception only allow from user space */
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lwp = lwp_self();
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if (lwp && fault_op)
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{
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__asm__ volatile("mrs %0, far_el1":"=r"(dfar));
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struct rt_aspace_fault_msg msg = {
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.fault_op = fault_op,
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.fault_type = fault_type,
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.fault_vaddr = dfar,
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};
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lwp_user_setting_save(rt_thread_self());
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__asm__ volatile("mrs %0, daif\nmsr daifclr, 0x3\nisb\n":"=r"(level));
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if (rt_aspace_fault_try_fix(lwp->aspace, &msg))
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{
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ret = 1;
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}
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__asm__ volatile("msr daif, %0\nisb\n"::"r"(level));
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}
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return ret;
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}
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#endif
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/**
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* this function will show registers of CPU
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*
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* @param regs the registers point
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*/
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void rt_hw_show_register(struct rt_hw_exp_stack *regs)
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{
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rt_kprintf("Execption:\n");
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rt_kprintf("X00:0x%16.16p X01:0x%16.16p X02:0x%16.16p X03:0x%16.16p\n", (void *)regs->x0, (void *)regs->x1, (void *)regs->x2, (void *)regs->x3);
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rt_kprintf("X04:0x%16.16p X05:0x%16.16p X06:0x%16.16p X07:0x%16.16p\n", (void *)regs->x4, (void *)regs->x5, (void *)regs->x6, (void *)regs->x7);
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rt_kprintf("X08:0x%16.16p X09:0x%16.16p X10:0x%16.16p X11:0x%16.16p\n", (void *)regs->x8, (void *)regs->x9, (void *)regs->x10, (void *)regs->x11);
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rt_kprintf("X12:0x%16.16p X13:0x%16.16p X14:0x%16.16p X15:0x%16.16p\n", (void *)regs->x12, (void *)regs->x13, (void *)regs->x14, (void *)regs->x15);
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rt_kprintf("X16:0x%16.16p X17:0x%16.16p X18:0x%16.16p X19:0x%16.16p\n", (void *)regs->x16, (void *)regs->x17, (void *)regs->x18, (void *)regs->x19);
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rt_kprintf("X20:0x%16.16p X21:0x%16.16p X22:0x%16.16p X23:0x%16.16p\n", (void *)regs->x20, (void *)regs->x21, (void *)regs->x22, (void *)regs->x23);
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rt_kprintf("X24:0x%16.16p X25:0x%16.16p X26:0x%16.16p X27:0x%16.16p\n", (void *)regs->x24, (void *)regs->x25, (void *)regs->x26, (void *)regs->x27);
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rt_kprintf("X28:0x%16.16p X29:0x%16.16p X30:0x%16.16p\n", (void *)regs->x28, (void *)regs->x29, (void *)regs->x30);
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rt_kprintf("SP_EL0:0x%16.16p\n", (void *)regs->sp_el0);
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rt_kprintf("SPSR :0x%16.16p\n", (void *)regs->cpsr);
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rt_kprintf("EPC :0x%16.16p\n", (void *)regs->pc);
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}
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#ifndef RT_USING_PIC
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void rt_hw_trap_irq(void)
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{
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#ifdef SOC_BCM283x
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extern rt_uint8_t core_timer_flag;
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void *param;
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uint32_t irq;
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rt_isr_handler_t isr_func;
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extern struct rt_irq_desc isr_table[];
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uint32_t value = 0;
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value = IRQ_PEND_BASIC & 0x3ff;
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if(core_timer_flag != 0)
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{
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uint32_t cpu_id = rt_hw_cpu_id();
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uint32_t int_source = CORE_IRQSOURCE(cpu_id);
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if (int_source & 0x0f)
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{
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if (int_source & 0x08)
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{
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isr_func = isr_table[IRQ_ARM_TIMER].handler;
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#ifdef RT_USING_INTERRUPT_INFO
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isr_table[IRQ_ARM_TIMER].counter++;
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#endif
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if (isr_func)
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{
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param = isr_table[IRQ_ARM_TIMER].param;
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isr_func(IRQ_ARM_TIMER, param);
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}
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}
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}
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}
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/* local interrupt*/
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if (value)
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{
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if (value & (1 << 8))
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{
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value = IRQ_PEND1;
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irq = __rt_ffs(value) - 1;
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}
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else if (value & (1 << 9))
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{
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value = IRQ_PEND2;
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irq = __rt_ffs(value) + 31;
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}
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else
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{
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value &= 0x0f;
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irq = __rt_ffs(value) + 63;
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}
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/* get interrupt service routine */
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isr_func = isr_table[irq].handler;
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#ifdef RT_USING_INTERRUPT_INFO
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isr_table[irq].counter++;
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#endif
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if (isr_func)
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{
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/* Interrupt for myself. */
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param = isr_table[irq].param;
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/* turn to interrupt service routine */
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isr_func(irq, param);
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}
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}
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#else
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void *param;
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int ir, ir_self;
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rt_isr_handler_t isr_func;
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extern struct rt_irq_desc isr_table[];
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ir = rt_hw_interrupt_get_irq();
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if (ir == 1023)
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{
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/* Spurious interrupt */
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return;
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}
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/* bit 10~12 is cpuid, bit 0~9 is interrupt id */
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ir_self = ir & 0x3ffUL;
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/* get interrupt service routine */
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isr_func = isr_table[ir_self].handler;
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#ifdef RT_USING_INTERRUPT_INFO
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isr_table[ir_self].counter++;
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#ifdef RT_USING_SMP
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isr_table[ir_self].cpu_counter[rt_hw_cpu_id()]++;
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#endif
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#endif
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if (isr_func)
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{
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/* Interrupt for myself. */
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param = isr_table[ir_self].param;
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/* turn to interrupt service routine */
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isr_func(ir_self, param);
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}
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/* end of interrupt */
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rt_hw_interrupt_ack(ir);
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#endif
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}
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#else
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void rt_hw_trap_irq(void)
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{
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rt_pic_do_traps();
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}
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#endif
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#ifdef RT_USING_SMART
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#define DBG_CHECK_EVENT(regs, esr) dbg_check_event(regs, esr)
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#else
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#define DBG_CHECK_EVENT(regs, esr) (0)
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#endif
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#ifndef RT_USING_PIC
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void rt_hw_trap_fiq(void)
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{
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void *param;
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int ir, ir_self;
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rt_isr_handler_t isr_func;
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extern struct rt_irq_desc isr_table[];
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ir = rt_hw_interrupt_get_irq();
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/* bit 10~12 is cpuid, bit 0~9 is interrup id */
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ir_self = ir & 0x3ffUL;
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/* get interrupt service routine */
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isr_func = isr_table[ir_self].handler;
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param = isr_table[ir_self].param;
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/* turn to interrupt service routine */
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isr_func(ir_self, param);
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/* end of interrupt */
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rt_hw_interrupt_ack(ir);
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}
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#else
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void rt_hw_trap_fiq(void)
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{
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rt_pic_do_traps();
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}
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#endif
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void print_exception(unsigned long esr, unsigned long epc);
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void SVC_Handler(struct rt_hw_exp_stack *regs);
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void rt_hw_trap_exception(struct rt_hw_exp_stack *regs)
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{
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unsigned long esr;
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unsigned char ec;
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asm volatile("mrs %0, esr_el1":"=r"(esr));
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ec = (unsigned char)((esr >> 26) & 0x3fU);
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if (DBG_CHECK_EVENT(regs, esr))
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{
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return;
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}
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else if (ec == 0x15) /* is 64bit syscall ? */
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{
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SVC_Handler(regs);
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/* never return here */
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}
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#ifdef RT_USING_SMART
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/**
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* Note: check_user_stack will take lock and it will possibly be a dead-lock
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* if exception comes from kernel.
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*/
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if ((regs->cpsr & 0x1f) == 0)
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{
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if (user_fault_fixable(esr, regs))
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return;
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}
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else
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{
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if (_irq_is_disable(regs->cpsr))
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{
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LOG_E("Kernel fault from interrupt/critical section");
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}
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if (rt_critical_level() != 0)
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{
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LOG_E("scheduler is not available");
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}
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else if (user_fault_fixable(esr, regs))
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return;
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}
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#endif
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print_exception(esr, regs->pc);
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rt_hw_show_register(regs);
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LOG_E("current thread: %s\n", rt_thread_self()->parent.name);
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#ifdef RT_USING_FINSH
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list_thread();
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#endif
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#ifdef RT_USING_LWP
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/* restore normal execution environment */
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__asm__ volatile("msr daifclr, 0x3\ndmb ishst\nisb\n");
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_check_fault(regs, 0, "user fault");
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#endif
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struct rt_hw_backtrace_frame frame = {.fp = regs->x29, .pc = regs->pc};
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rt_backtrace_frame(rt_thread_self(), &frame);
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rt_hw_cpu_shutdown();
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}
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void rt_hw_trap_serror(struct rt_hw_exp_stack *regs)
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{
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rt_kprintf("SError\n");
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rt_hw_show_register(regs);
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rt_kprintf("current: %s\n", rt_thread_self()->parent.name);
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#ifdef RT_USING_FINSH
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list_thread();
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#endif
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rt_hw_cpu_shutdown();
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}
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