928 lines
28 KiB
C
928 lines
28 KiB
C
/*!
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\file gd32f30x_fmc.c
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\brief FMC driver
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*/
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/*
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Copyright (C) 2017 GigaDevice
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2017-02-10, V1.0.1, firmware for GD32F30x
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*/
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#include "gd32f30x_fmc.h"
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/*!
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\brief set the wait state counter value
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\param[in] wscnt:wait state counter value
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\arg WS_WSCNT_0: FMC 0 wait
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\arg WS_WSCNT_1: FMC 1 wait
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\arg WS_WSCNT_2: FMC 2 wait
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\param[out] none
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\retval none
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*/
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void fmc_wscnt_set(uint32_t wscnt)
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{
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uint32_t reg;
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reg = FMC_WS;
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/* set the wait state counter value */
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reg &= ~FMC_WS_WSCNT;
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FMC_WS = (reg | wscnt);
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}
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/*!
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\brief unlock the main FMC operation
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\param[in] none
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\param[out] none
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\retval none
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*/
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void fmc_unlock(void)
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{
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if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){
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/* write the FMC unlock key */
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FMC_KEY0 = UNLOCK_KEY0;
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FMC_KEY0 = UNLOCK_KEY1;
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}
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if(FMC_BANK0_SIZE < FMC_SIZE){
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/* write the FMC unlock key */
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if(RESET != (FMC_CTL1 & FMC_CTL1_LK)){
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FMC_KEY1 = UNLOCK_KEY0;
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FMC_KEY1 = UNLOCK_KEY1;
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}
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}
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}
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/*!
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\brief unlock the FMC bank0 operation
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this function can be used for all GD32F20x devices.
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for GD32F20x with flash more than 512KB, this function unlocks bank0.
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for GD32F20x with flash no more than 512KB and it is equivalent to fmc_unlock function.
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\param[in] none
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\param[out] none
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\retval none
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*/
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void fmc_bank0_unlock(void)
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{
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if((RESET != (FMC_CTL0 & FMC_CTL0_LK))){
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/* write the FMC unlock key */
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FMC_KEY0 = UNLOCK_KEY0;
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FMC_KEY0 = UNLOCK_KEY1;
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}
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}
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/*!
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\brief unlock the FMC bank1 operation
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this function can be used for GD32F20x with flash more than 512KB.
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\param[in] none
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\param[out] none
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\retval none
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*/
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void fmc_bank1_unlock(void)
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{
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if((RESET != (FMC_CTL1 & FMC_CTL1_LK))){
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/* write the FMC unlock key */
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FMC_KEY1 = UNLOCK_KEY0;
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FMC_KEY1 = UNLOCK_KEY1;
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}
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}
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/*!
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\brief lock the main FMC operation
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\param[in] none
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\param[out] none
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\retval none
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*/
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void fmc_lock(void)
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{
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/* set the LK bit */
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FMC_CTL0 |= FMC_CTL0_LK;
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if(FMC_BANK0_SIZE < FMC_SIZE){
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/* set the LK bit */
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FMC_CTL1 |= FMC_CTL1_LK;
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}
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}
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/*!
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\brief lock the FMC bank0 operation
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this function can be used for all GD32F20X devices.
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for GD32F20x with flash more than 512KB, this function locks bank0.
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for GD32F20x with flash no more than 512KB and it is equivalent to fmc_lock function.
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\param[in] none
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\param[out] none
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\retval none
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*/
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void fmc_bank0_lock(void)
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{
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/* set the LK bit*/
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FMC_CTL0 |= FMC_CTL0_LK;
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}
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/*!
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\brief lock the FMC bank1 operation
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this function can be used for GD32F20x with flash more than 512KB.
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\param[in] none
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\param[out] none
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\retval none
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*/
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void fmc_bank1_lock(void)
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{
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/* set the LK bit*/
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FMC_CTL1 |= FMC_CTL1_LK;
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}
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/*!
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\brief erase page
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\param[in] page_address: the page address to be erased.
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\param[out] none
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\retval state of FMC, refer to fmc_state_enum
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*/
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fmc_state_enum fmc_page_erase(uint32_t page_address)
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{
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fmc_state_enum fmc_state;
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if(FMC_BANK0_SIZE < FMC_SIZE){
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if(FMC_BANK0_END_ADDRESS > page_address){
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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/* if the last operation is completed, start page erase */
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if(FMC_READY == fmc_state){
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FMC_CTL0 |= FMC_CTL0_PER;
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FMC_ADDR0 = page_address;
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FMC_CTL0 |= FMC_CTL0_START;
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/* wait for the FMC ready */
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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/* reset the PER bit */
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FMC_CTL0 &= ~FMC_CTL0_PER;
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}
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}else{
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/* wait for the FMC ready */
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fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
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/* if the last operation is completed, start page erase */
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if(FMC_READY == fmc_state){
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FMC_CTL1 |= FMC_CTL1_PER;
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FMC_ADDR1 = page_address;
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if(FMC_OBSTAT & FMC_OBSTAT_SPC){
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FMC_ADDR0 = page_address;
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}
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FMC_CTL1 |= FMC_CTL1_START;
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/* wait for the FMC ready */
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fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
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/* reset the PER bit */
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FMC_CTL1 &= ~FMC_CTL1_PER;
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}
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}
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}else{
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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/* if the last operation is completed, start page erase */
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if(FMC_READY == fmc_state){
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FMC_CTL0 |= FMC_CTL0_PER;
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FMC_ADDR0 = page_address;
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FMC_CTL0 |= FMC_CTL0_START;
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/* wait for the FMC ready */
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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/* reset the PER bit */
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FMC_CTL0 &= ~FMC_CTL0_PER;
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}
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}
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/* return the FMC state */
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return fmc_state;
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}
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/*!
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\brief erase whole chip
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\param[in] none
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\param[out] none
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\retval state of FMC, refer to fmc_state_enum
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*/
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fmc_state_enum fmc_mass_erase(void)
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{
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fmc_state_enum fmc_state;
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if(FMC_BANK0_SIZE < FMC_SIZE){
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/* wait for the FMC ready */
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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if(FMC_READY == fmc_state){
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/* start whole chip erase */
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FMC_CTL0 |= FMC_CTL0_MER;
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FMC_CTL0 |= FMC_CTL0_START;
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/* wait for the FMC ready */
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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/* reset the MER bit */
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FMC_CTL0 &= ~FMC_CTL0_MER;
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}
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fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
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if(FMC_READY == fmc_state){
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/* start whole chip erase */
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FMC_CTL1 |= FMC_CTL1_MER;
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FMC_CTL1 |= FMC_CTL1_START;
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/* wait for the FMC ready */
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fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
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/* reset the MER bit */
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FMC_CTL1 &= ~FMC_CTL1_MER;
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}
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}else{
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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if(FMC_READY == fmc_state){
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/* start whole chip erase */
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FMC_CTL0 |= FMC_CTL0_MER;
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FMC_CTL0 |= FMC_CTL0_START;
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/* wait for the FMC ready */
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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/* reset the MER bit */
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FMC_CTL0 &= ~FMC_CTL0_MER;
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}
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}
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/* return the FMC state */
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return fmc_state;
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}
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/*!
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\brief erase bank0
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\param[in] none
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\param[out] none
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\retval state of FMC, refer to fmc_state_enum
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*/
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fmc_state_enum fmc_bank0_erase(void)
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{
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fmc_state_enum fmc_state = FMC_READY;
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/* wait for the FMC ready */
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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if(FMC_READY == fmc_state){
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/* start FMC bank0 erase */
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FMC_CTL0 |= FMC_CTL0_MER;
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FMC_CTL0 |= FMC_CTL0_START;
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/* wait for the FMC ready */
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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/* reset the MER bit */
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FMC_CTL0 &= ~FMC_CTL0_MER;
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}
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/* return the fmc state */
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return fmc_state;
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}
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/*!
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\brief erase bank1
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\param[in] none
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\param[out] none
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\retval state of FMC, refer to fmc_state_enum
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*/
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fmc_state_enum fmc_bank1_erase(void)
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{
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fmc_state_enum fmc_state = FMC_READY;
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/* wait for the FMC ready */
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fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
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if(FMC_READY == fmc_state){
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/* start FMC bank1 erase */
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FMC_CTL1 |= FMC_CTL1_MER;
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FMC_CTL1 |= FMC_CTL1_START;
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/* wait for the FMC ready */
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fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
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/* reset the MER bit */
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FMC_CTL1 &= ~FMC_CTL1_MER;
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}
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/* return the fmc state */
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return fmc_state;
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}
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/*!
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\brief program a word at the corresponding address
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\param[in] address: address to program
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\param[in] data: word to program
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\param[out] none
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\retval state of FMC, refer to fmc_state_enum
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*/
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fmc_state_enum fmc_word_program(uint32_t address, uint32_t data)
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{
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fmc_state_enum fmc_state = FMC_READY;
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if(FMC_BANK0_SIZE < FMC_SIZE){
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if(FMC_BANK0_END_ADDRESS > address){
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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if(FMC_READY == fmc_state){
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/* set the PG bit to start program */
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FMC_CTL0 |= FMC_CTL0_PG;
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REG32(address) = data;
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/* wait for the FMC ready */
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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/* reset the PG bit */
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FMC_CTL0 &= ~FMC_CTL0_PG;
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}
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}else{
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fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
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if(FMC_READY == fmc_state){
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/* set the PG bit to start program */
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FMC_CTL1 |= FMC_CTL1_PG;
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REG32(address) = data;
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/* wait for the FMC ready */
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fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
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/* reset the PG bit */
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FMC_CTL1 &= ~FMC_CTL1_PG;
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}
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}
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}else{
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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if(FMC_READY == fmc_state){
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/* set the PG bit to start program */
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FMC_CTL0 |= FMC_CTL0_PG;
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REG32(address) = data;
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/* wait for the FMC ready */
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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/* reset the PG bit */
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FMC_CTL0 &= ~FMC_CTL0_PG;
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}
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}
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/* return the FMC state */
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return fmc_state;
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}
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/*!
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\brief program a half word at the corresponding address
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\param[in] address: address to program
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\param[in] data: halfword to program
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\param[out] none
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\retval state of FMC, refer to fmc_state_enum
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*/
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fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data)
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{
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fmc_state_enum fmc_state = FMC_READY;
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if(FMC_BANK0_SIZE < FMC_SIZE){
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if(FMC_BANK0_END_ADDRESS > address){
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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if(FMC_READY == fmc_state){
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/* set the PG bit to start program */
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FMC_CTL0 |= FMC_CTL0_PG;
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REG16(address) = data;
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/* wait for the FMC ready */
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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/* reset the PG bit */
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FMC_CTL0 &= ~FMC_CTL0_PG;
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}
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}else{
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fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
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if(FMC_READY == fmc_state){
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/* set the PG bit to start program */
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FMC_CTL1 |= FMC_CTL1_PG;
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REG16(address) = data;
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/* wait for the FMC ready */
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fmc_state = fmc_bank1_ready_wait(FMC_TIMEOUT_COUNT);
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/* reset the PG bit */
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FMC_CTL1 &= ~FMC_CTL1_PG;
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}
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}
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}else{
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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if(FMC_READY == fmc_state){
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/* set the PG bit to start program */
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FMC_CTL0 |= FMC_CTL0_PG;
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REG16(address) = data;
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/* wait for the FMC ready */
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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/* reset the PG bit */
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FMC_CTL0 &= ~FMC_CTL0_PG;
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}
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}
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/* return the FMC state */
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return fmc_state;
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}
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/*!
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\brief unlock the option byte operation
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\param[in] none
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\param[out] none
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\retval none
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*/
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void ob_unlock(void)
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{
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if(RESET == (FMC_CTL0 & FMC_CTL0_OBWEN)){
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/* write the FMC key */
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FMC_OBKEY = UNLOCK_KEY0;
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FMC_OBKEY = UNLOCK_KEY1;
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}
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}
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/*!
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\brief lock the option byte operation
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\param[in] none
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\param[out] none
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\retval none
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*/
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void ob_lock(void)
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{
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/* reset the OBWEN bit */
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FMC_CTL0 &= ~FMC_CTL0_OBWEN;
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}
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/*!
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\brief erase the FMC option byte
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unlock the FMC_CTL0 and option byte before calling this function
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\param[in] none
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\param[out] none
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\retval state of FMC, refer to fmc_state_enum
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*/
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fmc_state_enum ob_erase(void)
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{
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uint16_t temp_spc = FMC_NSPC;
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fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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/* check the option byte security protection value */
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if(RESET != ob_spc_get()){
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temp_spc = FMC_USPC;
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}
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if(FMC_READY == fmc_state){
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/* start erase the option byte */
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FMC_CTL0 |= FMC_CTL0_OBER;
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FMC_CTL0 |= FMC_CTL0_START;
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/* wait for the FMC ready */
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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if(FMC_READY == fmc_state){
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/* reset the OBER bit */
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FMC_CTL0 &= ~FMC_CTL0_OBER;
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/* set the OBPG bit */
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FMC_CTL0 |= FMC_CTL0_OBPG;
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/* no security protection */
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OB_SPC = (uint16_t)temp_spc;
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/* wait for the FMC ready */
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fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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if(FMC_TOERR != fmc_state){
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/* reset the OBPG bit */
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FMC_CTL0 &= ~FMC_CTL0_OBPG;
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}
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}else{
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if(FMC_TOERR != fmc_state){
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/* reset the OBPG bit */
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FMC_CTL0 &= ~FMC_CTL0_OBPG;
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}
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}
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}
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/* return the FMC state */
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return fmc_state;
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}
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/*!
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\brief enable write protection
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\param[in] ob_wp: specify sector to be write protected
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\arg OB_WPx(x=0..31): write protect specify sector
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\arg OB_WP_ALL: write protect all sector
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\param[out] none
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\retval state of FMC, refer to fmc_state_enum
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*/
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fmc_state_enum ob_write_protection_enable(uint32_t ob_wp)
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{
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uint16_t temp_wp0, temp_wp1, temp_wp2, temp_wp3;
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fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
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ob_wp = (uint32_t)(~ob_wp);
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temp_wp0 = (uint16_t)(ob_wp & OB_WP0_WP0);
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temp_wp1 = (uint16_t)((ob_wp & OB_WP1_WP1) >> 8U);
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temp_wp2 = (uint16_t)((ob_wp & OB_WP2_WP2) >> 16U);
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temp_wp3 = (uint16_t)((ob_wp & OB_WP3_WP3) >> 24U);
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if(FMC_READY == fmc_state){
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|
/* set the OBPG bit*/
|
|
FMC_CTL0 |= FMC_CTL0_OBPG;
|
|
|
|
if(0xFFU != temp_wp0){
|
|
OB_WP0 = temp_wp0;
|
|
|
|
/* wait for the FMC ready */
|
|
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
|
|
}
|
|
if((FMC_READY == fmc_state) && (0xFFU != temp_wp1)){
|
|
OB_WP1 = temp_wp1;
|
|
|
|
/* wait for the FMC ready */
|
|
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
|
|
}
|
|
if((FMC_READY == fmc_state) && (0xFFU != temp_wp2)){
|
|
OB_WP2 = temp_wp2;
|
|
|
|
/* wait for the FMC ready */
|
|
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
|
|
}
|
|
if((FMC_READY == fmc_state) && (0xFFU != temp_wp3)){
|
|
OB_WP3 = temp_wp3;
|
|
|
|
/* wait for the FMC ready */
|
|
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
|
|
}
|
|
if(FMC_TOERR != fmc_state){
|
|
/* reset the OBPG bit */
|
|
FMC_CTL0 &= ~FMC_CTL0_OBPG;
|
|
}
|
|
}
|
|
/* return the FMC state */
|
|
return fmc_state;
|
|
}
|
|
|
|
/*!
|
|
\brief configure security protection
|
|
\param[in] ob_spc: specify security protection
|
|
\arg FMC_NSPC: no security protection
|
|
\arg FMC_USPC: under security protection
|
|
\param[out] none
|
|
\retval state of FMC, refer to fmc_state_enum
|
|
*/
|
|
fmc_state_enum ob_security_protection_config(uint8_t ob_spc)
|
|
{
|
|
fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
|
|
|
|
if(FMC_READY == fmc_state){
|
|
FMC_CTL0 |= FMC_CTL0_OBER;
|
|
FMC_CTL0 |= FMC_CTL0_START;
|
|
|
|
/* wait for the FMC ready */
|
|
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
|
|
|
|
if(FMC_READY == fmc_state){
|
|
/* reset the OBER bit */
|
|
FMC_CTL0 &= ~FMC_CTL0_OBER;
|
|
|
|
/* start the option byte program */
|
|
FMC_CTL0 |= FMC_CTL0_OBPG;
|
|
|
|
OB_SPC = (uint16_t)ob_spc;
|
|
|
|
/* wait for the FMC ready */
|
|
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
|
|
|
|
if(FMC_TOERR != fmc_state){
|
|
/* reset the OBPG bit */
|
|
FMC_CTL0 &= ~FMC_CTL0_OBPG;
|
|
}
|
|
}else{
|
|
if(FMC_TOERR != fmc_state){
|
|
/* reset the OBER bit */
|
|
FMC_CTL0 &= ~FMC_CTL0_OBER;
|
|
}
|
|
}
|
|
}
|
|
/* return the FMC state */
|
|
return fmc_state;
|
|
}
|
|
|
|
/*!
|
|
\brief program the FMC user option byte
|
|
\param[in] ob_fwdgt: option byte watchdog value
|
|
\arg OB_FWDGT_SW: software free watchdog
|
|
\arg OB_FWDGT_HW: hardware free watchdog
|
|
\param[in] ob_deepsleep: option byte deepsleep reset value
|
|
\arg OB_DEEPSLEEP_NRST: no reset when entering deepsleep mode
|
|
\arg OB_DEEPSLEEP_RST: generate a reset instead of entering deepsleep mode
|
|
\param[in] ob_stdby:option byte standby reset value
|
|
\arg OB_STDBY_NRST: no reset when entering standby mode
|
|
\arg OB_STDBY_RST: generate a reset instead of entering standby mode
|
|
\param[in] ob_boot: specifies the option byte boot bank value
|
|
\arg OB_BOOT_B0: boot from bank0
|
|
\arg OB_BOOT_B1: boot from bank1 or bank0 if bank1 is void
|
|
\param[out] none
|
|
\retval state of FMC, refer to fmc_state_enum
|
|
*/
|
|
fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot)
|
|
{
|
|
fmc_state_enum fmc_state = FMC_READY;
|
|
uint8_t temp;
|
|
|
|
/* wait for the FMC ready */
|
|
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
|
|
|
|
if(FMC_READY == fmc_state){
|
|
/* set the OBPG bit*/
|
|
FMC_CTL0 |= FMC_CTL0_OBPG;
|
|
|
|
temp = ((uint8_t)((uint8_t)((uint8_t)(ob_boot | ob_fwdgt) | ob_deepsleep) | ob_stdby) | OB_USER_MASK);
|
|
OB_USER = (uint16_t)temp;
|
|
|
|
/* wait for the FMC ready */
|
|
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
|
|
|
|
if(FMC_TOERR != fmc_state){
|
|
/* reset the OBPG bit */
|
|
FMC_CTL0 &= ~FMC_CTL0_OBPG;
|
|
}
|
|
}
|
|
/* return the FMC state */
|
|
return fmc_state;
|
|
}
|
|
|
|
/*!
|
|
\brief program option bytes data
|
|
\param[in] address: the option bytes address to be programmed
|
|
\param[in] data: the byte to be programmed
|
|
\param[out] none
|
|
\retval state of FMC, refer to fmc_state_enum
|
|
*/
|
|
fmc_state_enum ob_data_program(uint32_t address, uint8_t data)
|
|
{
|
|
fmc_state_enum fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
|
|
|
|
if(FMC_READY == fmc_state){
|
|
/* set the OBPG bit */
|
|
FMC_CTL0 |= FMC_CTL0_OBPG;
|
|
REG16(address) = data;
|
|
|
|
/* wait for the FMC ready */
|
|
fmc_state = fmc_bank0_ready_wait(FMC_TIMEOUT_COUNT);
|
|
|
|
if(FMC_TOERR != fmc_state){
|
|
/* reset the OBPG bit */
|
|
FMC_CTL0 &= ~FMC_CTL0_OBPG;
|
|
}
|
|
}
|
|
/* return the FMC state */
|
|
return fmc_state;
|
|
}
|
|
|
|
/*!
|
|
\brief get the FMC user option byte
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval the FMC user option byte values
|
|
*/
|
|
uint8_t ob_user_get(void)
|
|
{
|
|
/* return the FMC user option byte value */
|
|
return (uint8_t)(FMC_OBSTAT >> 2U);
|
|
}
|
|
|
|
/*!
|
|
\brief get OB_DATA in register FMC_OBSTAT
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval ob_data
|
|
*/
|
|
uint16_t ob_data_get(void)
|
|
{
|
|
return (uint16_t)(FMC_OBSTAT >> 10U);
|
|
}
|
|
|
|
/*!
|
|
\brief get the FMC option byte write protection
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval the FMC write protection option byte value
|
|
*/
|
|
uint32_t ob_write_protection_get(void)
|
|
{
|
|
/* return the FMC write protection option byte value */
|
|
return FMC_WP;
|
|
}
|
|
|
|
/*!
|
|
\brief get the FMC option byte security protection
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval FlagStatus: SET or RESET
|
|
*/
|
|
FlagStatus ob_spc_get(void)
|
|
{
|
|
FlagStatus spc_state = RESET;
|
|
|
|
if(RESET != (FMC_OBSTAT & FMC_OBSTAT_SPC)){
|
|
spc_state = SET;
|
|
}else{
|
|
spc_state = RESET;
|
|
}
|
|
return spc_state;
|
|
}
|
|
|
|
/*!
|
|
\brief enable FMC interrupt
|
|
\param[in] interrupt: the FMC interrupt source
|
|
\arg FMC_INT_BANK0_END: enable FMC end of program interrupt
|
|
\arg FMC_INT_BANK0_ERR: enable FMC error interrupt
|
|
\arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt
|
|
\arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void fmc_interrupt_enable(uint32_t interrupt)
|
|
{
|
|
FMC_REG_VAL(interrupt) |= BIT(FMC_BIT_POS(interrupt));
|
|
}
|
|
|
|
/*!
|
|
\brief disable FMC interrupt
|
|
\param[in] interrupt: the FMC interrupt source
|
|
\arg FMC_INT_BANK0_END: enable FMC end of program interrupt
|
|
\arg FMC_INT_BANK0_ERR: enable FMC error interrupt
|
|
\arg FMC_INT_BANK1_END: enable FMC bank1 end of program interrupt
|
|
\arg FMC_INT_BANK1_ERR: enable FMC bank1 error interrupt
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void fmc_interrupt_disable(uint32_t interrupt)
|
|
{
|
|
FMC_REG_VAL(interrupt) &= ~BIT(FMC_BIT_POS(interrupt));
|
|
}
|
|
|
|
/*!
|
|
\brief check flag is set or not
|
|
\param[in] flag: check FMC flag
|
|
only one parameter can be selected which is shown as below:
|
|
\arg FMC_FLAG_BANK0_BUSY: FMC bank0 busy flag bit
|
|
\arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit
|
|
\arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit
|
|
\arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit
|
|
\arg FMC_FLAG_OBERR: FMC option bytes read error flag bit
|
|
\arg FMC_FLAG_BANK1_BUSY: FMC bank1 busy flag bit
|
|
\arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit
|
|
\arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit
|
|
\arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit
|
|
\param[out] none
|
|
\retval FlagStatus: SET or RESET
|
|
*/
|
|
FlagStatus fmc_flag_get(uint32_t flag)
|
|
{
|
|
if(RESET != (FMC_REG_VAL(flag) & BIT(FMC_BIT_POS(flag)))){
|
|
return SET;
|
|
}else{
|
|
return RESET;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief clear the FMC flag
|
|
\param[in] flag: clear FMC flag
|
|
only one parameter can be selected which is shown as below:
|
|
\arg FMC_FLAG_BANK0_PGERR: FMC bank0 operation error flag bit
|
|
\arg FMC_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error flag bit
|
|
\arg FMC_FLAG_BANK0_END: FMC bank0 end of operation flag bit
|
|
\arg FMC_FLAG_BANK1_PGERR: FMC bank1 operation error flag bit
|
|
\arg FMC_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error flag bit
|
|
\arg FMC_FLAG_BANK1_END: FMC bank1 end of operation flag bit
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void fmc_flag_clear(uint32_t flag)
|
|
{
|
|
FMC_REG_VAL(flag) |= BIT(FMC_BIT_POS(flag));
|
|
}
|
|
|
|
/*!
|
|
\brief get FMC interrupt flag state
|
|
\param[in] flag: FMC interrupt flags, refer to fmc_interrupt_flag_enum
|
|
only one parameter can be selected which is shown as below:
|
|
\arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit
|
|
\arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit
|
|
\arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit
|
|
\arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit
|
|
\arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit
|
|
\arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit
|
|
\param[out] none
|
|
\retval FlagStatus: SET or RESET
|
|
*/
|
|
FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag)
|
|
{
|
|
FlagStatus ret1 = RESET;
|
|
FlagStatus ret2 = RESET;
|
|
|
|
if(FMC_STAT0_REG_OFFSET == FMC_REG_OFFSET_GET(flag)){
|
|
/* get the staus of interrupt flag */
|
|
ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
|
|
/* get the staus of interrupt enale bit */
|
|
ret2 = (FlagStatus)(FMC_CTL0 & BIT(FMC_BIT_POS1(flag)));
|
|
}else{
|
|
/* get the staus of interrupt flag */
|
|
ret1 = (FlagStatus)(FMC_REG_VALS(flag) & BIT(FMC_BIT_POS0(flag)));
|
|
/* get the staus of interrupt enale bit */
|
|
ret2 = (FlagStatus)(FMC_CTL1 & BIT(FMC_BIT_POS1(flag)));
|
|
}
|
|
|
|
if(ret1 && ret2){
|
|
return SET;
|
|
}else{
|
|
return RESET;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
\brief clear FMC interrupt flag state
|
|
\param[in] flag: FMC interrupt flags, refer to can_interrupt_flag_enum
|
|
only one parameter can be selected which is shown as below:
|
|
\arg FMC_INT_FLAG_BANK0_PGERR: FMC bank0 operation error interrupt flag bit
|
|
\arg FMC_INT_FLAG_BANK0_WPERR: FMC bank0 erase/program protection error interrupt flag bit
|
|
\arg FMC_INT_FLAG_BANK0_END: FMC bank0 end of operation interrupt flag bit
|
|
\arg FMC_INT_FLAG_BANK1_PGERR: FMC bank1 operation error interrupt flag bit
|
|
\arg FMC_INT_FLAG_BANK1_WPERR: FMC bank1 erase/program protection error interrupt flag bit
|
|
\arg FMC_INT_FLAG_BANK1_END: FMC bank1 end of operation interrupt flag bit
|
|
\param[out] none
|
|
\retval none
|
|
*/
|
|
void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag)
|
|
{
|
|
FMC_REG_VALS(flag) |= BIT(FMC_BIT_POS0(flag));
|
|
}
|
|
|
|
/*!
|
|
\brief get the FMC bank0 state
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval state of FMC, refer to fmc_state_enum
|
|
*/
|
|
fmc_state_enum fmc_bank0_state_get(void)
|
|
{
|
|
fmc_state_enum fmc_state = FMC_READY;
|
|
|
|
if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_BUSY)){
|
|
fmc_state = FMC_BUSY;
|
|
}else{
|
|
if((uint32_t)0x00U != (FMC_STAT0 & FMC_STAT0_WPERR)){
|
|
fmc_state = FMC_WPERR;
|
|
}else{
|
|
if((uint32_t)0x00U != (FMC_STAT0 & (FMC_STAT0_PGERR))){
|
|
fmc_state = FMC_PGERR;
|
|
}
|
|
}
|
|
}
|
|
/* return the FMC state */
|
|
return fmc_state;
|
|
}
|
|
|
|
/*!
|
|
\brief get the FMC bank1 state
|
|
\param[in] none
|
|
\param[out] none
|
|
\retval state of FMC, refer to fmc_state_enum
|
|
*/
|
|
fmc_state_enum fmc_bank1_state_get(void)
|
|
{
|
|
fmc_state_enum fmc_state = FMC_READY;
|
|
|
|
if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_BUSY)){
|
|
fmc_state = FMC_BUSY;
|
|
}else{
|
|
if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_WPERR)){
|
|
fmc_state = FMC_WPERR;
|
|
}else{
|
|
if((uint32_t)0x00U != (FMC_STAT1 & FMC_STAT1_PGERR)){
|
|
fmc_state = FMC_PGERR;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* return the FMC state */
|
|
return fmc_state;
|
|
}
|
|
|
|
/*!
|
|
\brief check whether FMC bank0 is ready or not
|
|
\param[in] timeout: count of loop
|
|
\param[out] none
|
|
\retval state of FMC, refer to fmc_state_enum
|
|
*/
|
|
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout)
|
|
{
|
|
fmc_state_enum fmc_state = FMC_BUSY;
|
|
|
|
/* wait for FMC ready */
|
|
do{
|
|
/* get FMC state */
|
|
fmc_state = fmc_bank0_state_get();
|
|
timeout--;
|
|
}while((FMC_BUSY == fmc_state) && (0x00U != timeout));
|
|
|
|
if(FMC_BUSY == fmc_state){
|
|
fmc_state = FMC_TOERR;
|
|
}
|
|
/* return the FMC state */
|
|
return fmc_state;
|
|
}
|
|
|
|
/*!
|
|
\brief check whether FMC bank1 is ready or not
|
|
\param[in] timeout: count of loop
|
|
\param[out] none
|
|
\retval state of FMC, refer to fmc_state_enum
|
|
*/
|
|
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout)
|
|
{
|
|
fmc_state_enum fmc_state = FMC_BUSY;
|
|
|
|
/* wait for FMC ready */
|
|
do{
|
|
/* get FMC state */
|
|
fmc_state = fmc_bank1_state_get();
|
|
timeout--;
|
|
}while((FMC_BUSY == fmc_state) && (0x00U != timeout));
|
|
|
|
if(FMC_BUSY == fmc_state){
|
|
fmc_state = FMC_TOERR;
|
|
}
|
|
/* return the FMC state */
|
|
return fmc_state;
|
|
}
|