555 lines
16 KiB
C
555 lines
16 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fiopad_config.c
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-18 08:25:29
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* Description: This file is for io-pad function definition
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 huanghe 2021/11/5 init commit
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* 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec.
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*/
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/***************************** Include Files *********************************/
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#include "fiopad.h"
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#include "fparameters.h"
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#include "fdebug.h"
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#include "fpinctrl.h"
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#include "fassert.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define FIOPAD_DEBUG_TAG "FIOPAD-CFG"
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#define FIOPAD_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FIOPAD_WARN(format, ...) FT_DEBUG_PRINT_W(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FIOPAD_INFO(format, ...) FT_DEBUG_PRINT_I(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FIOPAD_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__)
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/************************** Function Prototypes ******************************/
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/*****************************************************************************/
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/**
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* @name: FIOPadSetSpimMux
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* @msg: set iopad mux for spim
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* @return {*}
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* @param {u32} spim_id, instance id of spi
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*/
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void FIOPadSetSpimMux(u32 spim_id)
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{
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if (FSPI2_ID == spim_id)
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{
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FPinSetFunc(FIOPAD_A29, FPIN_FUNC0); /* sclk */
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FPinSetFunc(FIOPAD_C29, FPIN_FUNC0); /* txd */
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FPinSetFunc(FIOPAD_C27, FPIN_FUNC0); /* rxd */
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FPinSetFunc(FIOPAD_A27, FPIN_FUNC0); /* csn0 */
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}
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}
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/**
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* @name: FIOPadSetGpioMux
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* @msg: set iopad mux for gpio
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* @return {*}
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* @param {u32} gpio_id, instance id of gpio
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* @param {u32} pin_id, index of pin
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*/
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void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id)
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{
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if (FGPIO3_ID == gpio_id)
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{
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switch (pin_id)
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{
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case 3: /* gpio 3-a-3 */
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FPinSetFunc(FIOPAD_A29, FPIN_FUNC6);
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break;
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case 4: /* gpio 3-a-4 */
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FPinSetFunc(FIOPAD_C29, FPIN_FUNC6);
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break;
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case 5: /* gpio 3-a-5 */
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FPinSetFunc(FIOPAD_C27, FPIN_FUNC6);
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break;
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case 6: /* gpio 3-a-6 */
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FPinSetFunc(FIOPAD_A27, FPIN_FUNC6);
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break;
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case 7: /* gpio 3-a-7 */ /*cannot use this pin*/
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FPinSetFunc(FIOPAD_AJ49, FPIN_FUNC6);
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break;
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case 8: /* gpio 3-a-8 */
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FPinSetFunc(FIOPAD_AL45, FPIN_FUNC6);
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break;
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case 9: /* gpio 3-a-9 */
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FPinSetFunc(FIOPAD_AL43, FPIN_FUNC6);
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break;
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default:
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break;
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}
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}
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else if (FGPIO4_ID == gpio_id)
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{
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switch (pin_id)
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{
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case 5: /* gpio 4-a-5 */
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FPinSetFunc(FIOPAD_W47, FPIN_FUNC6);
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break;
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case 9: /* gpio 4-a-9 */
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FPinSetFunc(FIOPAD_U49, FPIN_FUNC6);
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break;
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case 10: /* gpio 4-a-10 */
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FPinSetFunc(FIOPAD_AE45, FPIN_FUNC6);
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break;
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case 11: /* gpio 4-a-11 */
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FPinSetFunc(FIOPAD_AC45, FPIN_FUNC6);
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break;
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case 12: /* gpio 4-a-12 */
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FPinSetFunc(FIOPAD_AE43, FPIN_FUNC6);
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break;
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case 13: /* gpio 4-a-13 */
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FPinSetFunc(FIOPAD_AA43, FPIN_FUNC6);
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break;
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default:
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break;
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}
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}
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}
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/**
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* @name: FIOPadSetCanMux
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* @msg: set iopad mux for can
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* @return {*}
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* @param {u32} can_id, instance id of can
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*/
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void FIOPadSetCanMux(u32 can_id)
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{
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if (can_id == FCAN0_ID)
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{
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/* can0 */
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FPinSetFunc(FIOPAD_A37, FPIN_FUNC0); /* can0-tx: func 0 */
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FPinSetFunc(FIOPAD_A39, FPIN_FUNC0); /* can0-rx: func 0 */
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}
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else if (can_id == FCAN1_ID)
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{
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/* can1 */
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FPinSetFunc(FIOPAD_A41, FPIN_FUNC0); /* can1-tx: func 0 */
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FPinSetFunc(FIOPAD_C41, FPIN_FUNC0); /* can1-rx: func 0 */
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}
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else
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{
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FIOPAD_ERROR("can id is error.\r\n");
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}
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}
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/**
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* @name: FIOPadSetQspiMux
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* @msg: set iopad mux for qspi
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* @return {*}
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* @param {u32} qspi_id, id of qspi instance
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* @param {u32} cs_id, id of qspi cs
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*/
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void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id)
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{
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if (qspi_id == FQSPI0_ID)
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{
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/* add sck, io0-io3 iopad multiplex */
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}
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if (cs_id == FQSPI_CS_0)
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{
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FPinSetFunc(FIOPAD_AR51, FPIN_FUNC0);
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}
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else if (cs_id == FQSPI_CS_1)
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{
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FPinSetFunc(FIOPAD_AR45, FPIN_FUNC0);
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}
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else if (cs_id == FQSPI_CS_2)
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{
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FPinSetFunc(FIOPAD_C33, FPIN_FUNC5);
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}
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else if (cs_id == FQSPI_CS_3)
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{
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FPinSetFunc(FIOPAD_A33, FPIN_FUNC5);
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}
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else
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{
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FIOPAD_ERROR("can id is error.\r\n");
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}
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}
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/**
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* @name: FIOPadSetPwmMux
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* @msg: set iopad mux for pwm
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* @return {*}
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* @param {u32} pwm_id, id of pwm instance
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* @param {u32} pwm_channel, channel of pwm instance
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*/
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void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel)
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{
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FASSERT(pwm_id < FPWM_NUM);
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FASSERT(pwm_channel < FPWM_CHANNEL_NUM);
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switch (pwm_id)
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{
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case FPWM0_ID:
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if (pwm_channel == 0)
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{
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FPinSetFunc(FIOPAD_AL55, FPIN_FUNC1); /* PWM0_OUT: func 1 */
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}
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if (pwm_channel == 1)
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{
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FPinSetFunc(FIOPAD_AJ53, FPIN_FUNC1); /* PWM1_OUT: func 1 */
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}
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break;
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case FPWM1_ID:
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if (pwm_channel == 0)
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{
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FPinSetFunc(FIOPAD_AG53, FPIN_FUNC1); /* PWM2_OUT: func 1 */
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}
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if (pwm_channel == 1)
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{
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FPinSetFunc(FIOPAD_AC55, FPIN_FUNC1); /* PWM3_OUT: func 1 */
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}
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break;
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case FPWM2_ID:
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if (pwm_channel == 0)
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{
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FPinSetFunc(FIOPAD_BA51, FPIN_FUNC1); /* PWM4_OUT: func 1 */
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}
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if (pwm_channel == 1)
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{
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FPinSetFunc(FIOPAD_C35, FPIN_FUNC2); /* PWM5_OUT: func 2 */
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}
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break;
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case FPWM3_ID:
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if (pwm_channel == 0)
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{
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FPinSetFunc(FIOPAD_A33, FPIN_FUNC2); /* PWM6_OUT: func 2 */
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}
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if (pwm_channel == 1)
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{
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FPinSetFunc(FIOPAD_A39, FPIN_FUNC2); /* PWM7_OUT: func 2 */
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}
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break;
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case FPWM4_ID:
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if (pwm_channel == 0)
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{
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FPinSetFunc(FIOPAD_C41, FPIN_FUNC2); /* PWM8_OUT: func 2 */
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}
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if (pwm_channel == 1)
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{
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FPinSetFunc(FIOPAD_A45, FPIN_FUNC2); /* PWM9_OUT: func 2 */
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}
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break;
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case FPWM5_ID:
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if (pwm_channel == 0)
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{
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FPinSetFunc(FIOPAD_A47, FPIN_FUNC2); /* PWM10_OUT: func 2 */
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}
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if (pwm_channel == 1)
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{
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FPinSetFunc(FIOPAD_C29, FPIN_FUNC2); /* PWM11_OUT: func 2 */
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}
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break;
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case FPWM6_ID:
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if (pwm_channel == 0)
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{
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FPinSetFunc(FIOPAD_A27, FPIN_FUNC2); /* PWM12_OUT: func 2 */
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}
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if (pwm_channel == 1)
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{
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FPinSetFunc(FIOPAD_J35, FPIN_FUNC3); /* PWM13_OUT: func 3 */
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}
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break;
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case FPWM7_ID:
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if (pwm_channel == 0)
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{
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FPinSetFunc(FIOPAD_E39, FPIN_FUNC3); /* PWM14_OUT: func 3 */
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}
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if (pwm_channel == 1)
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{
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FPinSetFunc(FIOPAD_C39, FPIN_FUNC3); /* PWM15_OUT: func 3 */
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}
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break;
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default:
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FIOPAD_ERROR("pwm id is error.\r\n");
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break;
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}
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}
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/**
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* @name: FIOPadSetAdcMux
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* @msg: set iopad mux for adc
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* @return {*}
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* @param {u32} adc_id, id of adc instance
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* @param {u32} adc_channel, id of adc channel
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*/
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void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel)
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{
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if (adc_id == FADC0_ID)
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{
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switch (adc_channel)
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{
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case FADC_CHANNEL_0:
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FPinSetFunc(FIOPAD_R47, FPIN_FUNC7); /* adc0-0: func 7 */
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break;
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case FADC_CHANNEL_1:
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FPinSetFunc(FIOPAD_R45, FPIN_FUNC7); /* adc0-1: func 7 */
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break;
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case FADC_CHANNEL_2:
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FPinSetFunc(FIOPAD_N47, FPIN_FUNC7); /* adc0-2: func 7 */
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break;
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case FADC_CHANNEL_3:
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FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-3: func 7 */
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break;
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case FADC_CHANNEL_4:
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FPinSetFunc(FIOPAD_L51, FPIN_FUNC7); /* adc0-4: func 7 */
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break;
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case FADC_CHANNEL_5:
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FPinSetFunc(FIOPAD_J51, FPIN_FUNC7); /* adc0-5: func 7 */
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break;
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case FADC_CHANNEL_6:
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FPinSetFunc(FIOPAD_J41, FPIN_FUNC7); /* adc0-6: func 7 */
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break;
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case FADC_CHANNEL_7:
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FPinSetFunc(FIOPAD_E43, FPIN_FUNC7); /* adc0-7: func 7 */
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break;
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default:
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FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
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break;
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}
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}
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else
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{
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FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel);
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}
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}
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/**
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* @name: FIOPadSetMioMux
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* @msg: set iopad mux for mio
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* @return {*}
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* @param {u32} mio_id, instance id of i2c
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*/
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void FIOPadSetMioMux(u32 mio_id)
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{
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switch (mio_id)
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{
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case FMIO0_ID:
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{
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FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */
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FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */
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}
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break;
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case FMIO1_ID:
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{
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FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */
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FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */
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}
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break;
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case FMIO2_ID:
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{
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FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */
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FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */
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}
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break;
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case FMIO3_ID:
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{
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FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */
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FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */
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}
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break;
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case FMIO4_ID:
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{
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FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */
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FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */
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}
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break;
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case FMIO5_ID:
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{
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FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */
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FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */
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}
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break;
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case FMIO6_ID:
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{
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FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */
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FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */
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}
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break;
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case FMIO7_ID:
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{
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FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */
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FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */
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}
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break;
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case FMIO8_ID:
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{
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FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */
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FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */
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}
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break;
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case FMIO9_ID:
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{
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FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */
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FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */
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}
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break;
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case FMIO10_ID:
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{
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FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */
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FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */
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}
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break;
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case FMIO11_ID:
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{
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FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */
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FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */
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}
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break;
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case FMIO12_ID:
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{
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FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */
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FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */
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}
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break;
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case FMIO13_ID:
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{
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FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */
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FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */
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}
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break;
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case FMIO14_ID:
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{
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FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */
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FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */
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}
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break;
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case FMIO15_ID:
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{
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FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */
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FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */
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}
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break;
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default:
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break;
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}
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}
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/**
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* @name: FIOPadSetTachoMux
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* @msg: set iopad mux for pwm_in
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* @return {*}
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* @param {u32} pwm_in_id, instance id of tacho
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*/
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void FIOPadSetTachoMux(u32 pwm_in_id)
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{
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switch (pwm_in_id)
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{
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case FTACHO0_ID:
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FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1);
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break;
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case FTACHO1_ID:
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FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1);
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break;
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case FTACHO2_ID:
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FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1);
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break;
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case FTACHO3_ID:
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FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1);
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break;
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case FTACHO4_ID:
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FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1);
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break;
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case FTACHO5_ID:
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FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1);
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break;
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case FTACHO6_ID:
|
||
FPinSetFunc(FIOPAD_C33, FPIN_FUNC2);
|
||
break;
|
||
case FTACHO7_ID:
|
||
FPinSetFunc(FIOPAD_A37, FPIN_FUNC2);
|
||
break;
|
||
case FTACHO8_ID:
|
||
FPinSetFunc(FIOPAD_A41, FPIN_FUNC2);
|
||
break;
|
||
case FTACHO9_ID:
|
||
FPinSetFunc(FIOPAD_A43, FPIN_FUNC2);
|
||
break;
|
||
case FTACHO10_ID:
|
||
FPinSetFunc(FIOPAD_C45, FPIN_FUNC2);
|
||
break;
|
||
case FTACHO11_ID:
|
||
FPinSetFunc(FIOPAD_A29, FPIN_FUNC2);
|
||
break;
|
||
case FTACHO12_ID:
|
||
FPinSetFunc(FIOPAD_C27, FPIN_FUNC2);
|
||
break;
|
||
case FTACHO13_ID:
|
||
FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2);
|
||
break;
|
||
case FTACHO14_ID:
|
||
FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2);
|
||
break;
|
||
case FTACHO15_ID:
|
||
FPinSetFunc(FIOPAD_G55, FPIN_FUNC2);
|
||
break;
|
||
default:
|
||
break;
|
||
}
|
||
}
|
||
|
||
/**
|
||
* @name: FIOPadSetUartMux
|
||
* @msg: set iopad mux for uart
|
||
* @return {*}
|
||
* @param {u32} uart_id, instance id of uart
|
||
*/
|
||
void FIOPadSetUartMux(u32 uart_id)
|
||
{
|
||
switch (uart_id)
|
||
{
|
||
case FUART0_ID:
|
||
FPinSetFunc(FIOPAD_J33, FPIN_FUNC4);
|
||
FPinSetFunc(FIOPAD_J35, FPIN_FUNC4);
|
||
break;
|
||
case FUART1_ID:
|
||
FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0);
|
||
FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0);
|
||
break;
|
||
case FUART2_ID:
|
||
FPinSetFunc(FIOPAD_A43, FPIN_FUNC0);
|
||
FPinSetFunc(FIOPAD_A45, FPIN_FUNC0);
|
||
break;
|
||
case FUART3_ID:
|
||
FPinSetFunc(FIOPAD_L33, FPIN_FUNC2);
|
||
FPinSetFunc(FIOPAD_N31, FPIN_FUNC2);
|
||
break;
|
||
default:
|
||
break;
|
||
}
|
||
} |