316 lines
12 KiB
C
316 lines
12 KiB
C
/*""FILE COMMENT""*******************************************************
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* System Name : API for RX62Nxx
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* File Name : r_pdl_common_defs_RX62Nxx.h
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* Version : 1.02
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* Contents : API common definitions
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* Customer :
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* Model :
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* Order :
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* CPU : RX
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* Compiler : RXC
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* OS : Nothing
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* Programmer :
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* Note :
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************************************************************************
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* Copyright, 2011. Renesas Electronics Corporation
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* and Renesas Solutions Corporation
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************************************************************************
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* History : 2011.04.08
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* : Ver 1.02
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* : CS-5 release.
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*""FILE COMMENT END""**************************************************/
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#ifndef R_PDL_COMMON_DEFS_RX62Nxx_H
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#define R_PDL_COMMON_DEFS_RX62Nxx_H
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#include <stdint.h>
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#include <stdbool.h>
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#include <machine.h>
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#include <stddef.h>
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#include <iorx62n.h>
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/* Callback function type */
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typedef void (* VoidCallBackFunc)(void);
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/* The supported MCU group */
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#define PDL_MCU_GROUP RX62N
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/* The highest interrupt priority level */
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#define IPL_MAX 15
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/* Use the I/O register area to indicate that a callback function pointer is not to be used */
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#define PDL_NO_FUNC (VoidCallBackFunc)0x00080000ul
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/* Use the ROM area to indicate that a data pointer is not to be used */
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#define PDL_NO_PTR (void *)0xFFFFFFFCul
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/* When no parameters options are required */
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#define PDL_NO_DATA 0
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/* Shared global variables */
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extern volatile uint32_t rpdl_CGC_f_pclk;
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extern volatile uint32_t rpdl_CGC_f_iclk;
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extern volatile uint32_t rpdl_CGC_f_bclk;
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extern volatile uint8_t rpdl_INTC_brk_command;
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extern volatile uint8_t rpdl_INTC_brk_data8;
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extern volatile uint32_t rpdl_INTC_saved_isp;
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/* Shared functions */
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uint8_t rpdl_DMAC_get_channel(const uint8_t);
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/* Utility functions */
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uint8_t rpdl_BCD8_to_dec(const uint8_t);
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uint16_t rpdl_BCD16_to_dec(const uint16_t);
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bool rpdl_common_BCD8_check(const uint8_t);
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bool rpdl_common_BCD16_check(const uint16_t);
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bool rpdl_common_BCD32_check(const uint32_t);
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/* BRK handler command options */
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typedef enum {
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BRK_NO_COMMAND,
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BRK_START_ADC_10,
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BRK_START_ADC_10_AND_SLEEP,
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BRK_SLEEP,
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BRK_ALL_MODULE_CLOCK_STOP,
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BRK_STANDBY,
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BRK_DEEP_STANDBY,
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BRK_LOAD_FINTV_REGISTER,
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BRK_WRITE_IPL,
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BRK_CMT_START,
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BRK_CMT_STOP
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} brk_commands;
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/* Bit definitions */
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#define BIT_0 0x00000001ul
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#define BIT_1 0x00000002ul
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#define BIT_2 0x00000004ul
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#define BIT_3 0x00000008ul
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#define BIT_4 0x00000010ul
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#define BIT_5 0x00000020ul
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#define BIT_6 0x00000040ul
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#define BIT_7 0x00000080ul
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#define BIT_8 0x00000100ul
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#define BIT_9 0x00000200ul
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#define BIT_10 0x00000400ul
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#define BIT_11 0x00000800ul
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#define BIT_12 0x00001000ul
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#define BIT_13 0x00002000ul
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#define BIT_14 0x00004000ul
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#define BIT_15 0x00008000ul
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#define BIT_16 0x00010000ul
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#define BIT_17 0x00020000ul
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#define BIT_18 0x00040000ul
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#define BIT_19 0x00080000ul
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#define BIT_20 0x00100000ul
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#define BIT_21 0x00200000ul
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#define BIT_22 0x00400000ul
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#define BIT_23 0x00800000ul
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#define BIT_24 0x01000000ul
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#define BIT_25 0x02000000ul
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#define BIT_26 0x04000000ul
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#define BIT_27 0x08000000ul
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#define BIT_28 0x10000000ul
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#define BIT_29 0x20000000ul
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#define BIT_30 0x40000000ul
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#define BIT_31 0x80000000ul
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#define INV_BIT_0 0xFFFFFFFEul
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#define INV_BIT_1 0xFFFFFFFDul
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#define INV_BIT_2 0xFFFFFFFBul
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#define INV_BIT_3 0xFFFFFFF7ul
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#define INV_BIT_4 0xFFFFFFEFul
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#define INV_BIT_5 0xFFFFFFDFul
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#define INV_BIT_6 0xFFFFFFBFul
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#define INV_BIT_7 0xFFFFFF7Ful
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#define INV_BIT_8 0xFFFFFEFFul
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#define INV_BIT_9 0xFFFFFDFFul
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#define INV_BIT_10 0xFFFFFBFFul
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#define INV_BIT_11 0xFFFFF7FFul
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#define INV_BIT_12 0xFFFFEFFFul
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#define INV_BIT_13 0xFFFFDFFFul
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#define INV_BIT_14 0xFFFFBFFFul
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#define INV_BIT_15 0xFFFF7FFFul
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#define INV_BIT_16 0xFFFEFFFFul
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#define INV_BIT_17 0xFFFDFFFFul
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#define INV_BIT_18 0xFFFBFFFFul
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#define INV_BIT_19 0xFFF7FFFFul
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#define INV_BIT_20 0xFFEFFFFFul
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#define INV_BIT_21 0xFFDFFFFFul
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#define INV_BIT_22 0xFFBFFFFFul
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#define INV_BIT_23 0xFF7FFFFFul
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#define INV_BIT_24 0xFEFFFFFFul
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#define INV_BIT_25 0xFDFFFFFFul
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#define INV_BIT_26 0xFBFFFFFFul
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#define INV_BIT_27 0xF7FFFFFFul
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#define INV_BIT_28 0xEFFFFFFFul
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#define INV_BIT_29 0xDFFFFFFFul
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#define INV_BIT_30 0xBFFFFFFFul
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#define INV_BIT_31 0x7FFFFFFFul
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/* Interrupt vector numbers */
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#define PDL_INTC_VECTOR_BUSERR VECT_BSC_BUSERR
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#define PDL_INTC_VECTOR_FIFERR VECT_FCU_FIFERR
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#define PDL_INTC_VECTOR_FRDYI VECT_FCU_FRDYI
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#define PDL_INTC_VECTOR_SWINT VECT_ICU_SWINT
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#define PDL_INTC_VECTOR_CMT0 VECT_CMT0_CMI0
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#define PDL_INTC_VECTOR_CMT1 VECT_CMT1_CMI1
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#define PDL_INTC_VECTOR_CMT2 VECT_CMT2_CMI2
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#define PDL_INTC_VECTOR_CMT3 VECT_CMT3_CMI3
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#define PDL_INTC_VECTOR_EINT VECT_ETHER_EINT
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#define PDL_INTC_VECTOR_D0FIFO0 VECT_USB0_D0FIFO0
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#define PDL_INTC_VECTOR_D1FIFO0 VECT_USB0_D1FIFO0
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#define PDL_INTC_VECTOR_USBI0 VECT_USB0_USBI0
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#define PDL_INTC_VECTOR_USBR0 VECT_USB_USBR0
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#define PDL_INTC_VECTOR_D0FIFO1 VECT_USB1_D0FIFO1
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#define PDL_INTC_VECTOR_D1FIFO1 VECT_USB1_D1FIFO1
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#define PDL_INTC_VECTOR_USBI1 VECT_USB1_USBI1
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#define PDL_INTC_VECTOR_USBR1 VECT_USB_USBR1
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#define PDL_INTC_VECTOR_SPEI0 VECT_RSPI0_SPEI0
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#define PDL_INTC_VECTOR_SPRI0 VECT_RSPI0_SPRI0
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#define PDL_INTC_VECTOR_SPTI0 VECT_RSPI0_SPTI0
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#define PDL_INTC_VECTOR_SPII0 VECT_RSPI0_SPII0
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#define PDL_INTC_VECTOR_SPEI1 VECT_RSPI1_SPEI1
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#define PDL_INTC_VECTOR_SPRI1 VECT_RSPI1_SPRI1
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#define PDL_INTC_VECTOR_SPTI1 VECT_RSPI1_SPTI1
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#define PDL_INTC_VECTOR_SPII1 VECT_RSPI1_SPII1
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#define PDL_INTC_VECTOR_ERS0 VECT_CAN0_ERS0
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#define PDL_INTC_VECTOR_RXF0 VECT_CAN0_RXF0
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#define PDL_INTC_VECTOR_TXF0 VECT_CAN0_TXF0
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#define PDL_INTC_VECTOR_RXM0 VECT_CAN0_RXM0
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#define PDL_INTC_VECTOR_TXM0 VECT_CAN0_TXM0
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#define PDL_INTC_VECTOR_PRD VECT_RTC_PRD
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#define PDL_INTC_VECTOR_CUP VECT_RTC_CUP
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#define PDL_INTC_VECTOR_ALM VECT_RTC_ALM
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#define PDL_INTC_VECTOR_IRQ0 VECT_ICU_IRQ0
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#define PDL_INTC_VECTOR_IRQ1 VECT_ICU_IRQ1
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#define PDL_INTC_VECTOR_IRQ2 VECT_ICU_IRQ2
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#define PDL_INTC_VECTOR_IRQ3 VECT_ICU_IRQ3
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#define PDL_INTC_VECTOR_IRQ4 VECT_ICU_IRQ4
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#define PDL_INTC_VECTOR_IRQ5 VECT_ICU_IRQ5
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#define PDL_INTC_VECTOR_IRQ6 VECT_ICU_IRQ6
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#define PDL_INTC_VECTOR_IRQ7 VECT_ICU_IRQ7
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#define PDL_INTC_VECTOR_IRQ8 VECT_ICU_IRQ8
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#define PDL_INTC_VECTOR_IRQ9 VECT_ICU_IRQ9
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#define PDL_INTC_VECTOR_IRQ10 VECT_ICU_IRQ10
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#define PDL_INTC_VECTOR_IRQ11 VECT_ICU_IRQ11
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#define PDL_INTC_VECTOR_IRQ12 VECT_ICU_IRQ12
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#define PDL_INTC_VECTOR_IRQ13 VECT_ICU_IRQ13
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#define PDL_INTC_VECTOR_IRQ14 VECT_ICU_IRQ14
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#define PDL_INTC_VECTOR_IRQ15 VECT_ICU_IRQ15
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#define PDL_INTC_VECTOR_WOVI VECT_WDT_WOVI
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#define PDL_INTC_VECTOR_ADI0 VECT_AD0_ADI0
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#define PDL_INTC_VECTOR_ADI1 VECT_AD1_ADI1
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#define PDL_INTC_VECTOR_ADI12_0 VECT_S12AD_ADI
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#define PDL_INTC_VECTOR_TGIA0 VECT_MTU0_TGIA0
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#define PDL_INTC_VECTOR_TGIB0 VECT_MTU0_TGIB0
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#define PDL_INTC_VECTOR_TGIC0 VECT_MTU0_TGIC0
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#define PDL_INTC_VECTOR_TGID0 VECT_MTU0_TGID0
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#define PDL_INTC_VECTOR_TCIV0 VECT_MTU0_TCIV0
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#define PDL_INTC_VECTOR_TGIE0 VECT_MTU0_TGIE0
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#define PDL_INTC_VECTOR_TGIF0 VECT_MTU0_TGIF0
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#define PDL_INTC_VECTOR_TGIA1 VECT_MTU1_TGIA1
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#define PDL_INTC_VECTOR_TGIB1 VECT_MTU1_TGIB1
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#define PDL_INTC_VECTOR_TCIV1 VECT_MTU1_TCIV1
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#define PDL_INTC_VECTOR_TCIU1 VECT_MTU1_TCIU1
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#define PDL_INTC_VECTOR_TGIA2 VECT_MTU2_TGIA2
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#define PDL_INTC_VECTOR_TGIB2 VECT_MTU2_TGIB2
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#define PDL_INTC_VECTOR_TCIV2 VECT_MTU2_TCIV2
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#define PDL_INTC_VECTOR_TCIU2 VECT_MTU2_TCIU2
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#define PDL_INTC_VECTOR_TGIA3 VECT_MTU3_TGIA3
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#define PDL_INTC_VECTOR_TGIB3 VECT_MTU3_TGIB3
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#define PDL_INTC_VECTOR_TGIC3 VECT_MTU3_TGIC3
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#define PDL_INTC_VECTOR_TGID3 VECT_MTU3_TGID3
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#define PDL_INTC_VECTOR_TCIV3 VECT_MTU3_TCIV3
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#define PDL_INTC_VECTOR_TGIA4 VECT_MTU4_TGIA4
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#define PDL_INTC_VECTOR_TGIB4 VECT_MTU4_TGIB4
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#define PDL_INTC_VECTOR_TGIC4 VECT_MTU4_TGIC4
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#define PDL_INTC_VECTOR_TGID4 VECT_MTU4_TGID4
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#define PDL_INTC_VECTOR_TCIV4 VECT_MTU4_TCIV4
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#define PDL_INTC_VECTOR_TGIU5 VECT_MTU5_TGIU5
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#define PDL_INTC_VECTOR_TGIV5 VECT_MTU5_TGIV5
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#define PDL_INTC_VECTOR_TGIW5 VECT_MTU5_TGIW5
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#define PDL_INTC_VECTOR_TGIA6 VECT_MTU6_TGIA6
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#define PDL_INTC_VECTOR_TGIB6 VECT_MTU6_TGIB6
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#define PDL_INTC_VECTOR_TGIC6 VECT_MTU6_TGIC6
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#define PDL_INTC_VECTOR_TGID6 VECT_MTU6_TGID6
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#define PDL_INTC_VECTOR_TCIV6 VECT_MTU6_TCIV6
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#define PDL_INTC_VECTOR_TGIE6 VECT_MTU6_TGIE6
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#define PDL_INTC_VECTOR_TGIF6 VECT_MTU6_TGIF6
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#define PDL_INTC_VECTOR_TGIA7 VECT_MTU7_TGIA7
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#define PDL_INTC_VECTOR_TGIB7 VECT_MTU7_TGIB7
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#define PDL_INTC_VECTOR_TCIV7 VECT_MTU7_TCIV7
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#define PDL_INTC_VECTOR_TCIU7 VECT_MTU7_TCIU7
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#define PDL_INTC_VECTOR_TGIA8 VECT_MTU8_TGIA8
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#define PDL_INTC_VECTOR_TGIB8 VECT_MTU8_TGIB8
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#define PDL_INTC_VECTOR_TCIV8 VECT_MTU8_TCIV8
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#define PDL_INTC_VECTOR_TCIU8 VECT_MTU8_TCIU8
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#define PDL_INTC_VECTOR_TGIA9 VECT_MTU9_TGIA9
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#define PDL_INTC_VECTOR_TGIB9 VECT_MTU9_TGIB9
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#define PDL_INTC_VECTOR_TGIC9 VECT_MTU9_TGIC9
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#define PDL_INTC_VECTOR_TGID9 VECT_MTU9_TGID9
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#define PDL_INTC_VECTOR_TCIV9 VECT_MTU9_TCIV9
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#define PDL_INTC_VECTOR_TGIA10 VECT_MTU10_TGIA10
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#define PDL_INTC_VECTOR_TGIB10 VECT_MTU10_TGIB10
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#define PDL_INTC_VECTOR_TGIC10 VECT_MTU10_TGIC10
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#define PDL_INTC_VECTOR_TGID10 VECT_MTU10_TGID10
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#define PDL_INTC_VECTOR_TCIV10 VECT_MTU10_TCIV10
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#define PDL_INTC_VECTOR_TGIU11 VECT_MTU11_TGIU11
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#define PDL_INTC_VECTOR_TGIV11 VECT_MTU11_TGIV11
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#define PDL_INTC_VECTOR_TGIW11 VECT_MTU11_TGIW11
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#define PDL_INTC_VECTOR_OEI1 VECT_POE_OEI1
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#define PDL_INTC_VECTOR_OEI2 VECT_POE_OEI2
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#define PDL_INTC_VECTOR_OEI3 VECT_POE_OEI3
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#define PDL_INTC_VECTOR_OEI4 VECT_POE_OEI4
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#define PDL_INTC_VECTOR_CMIA0 VECT_TMR0_CMIA0
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#define PDL_INTC_VECTOR_CMIB0 VECT_TMR0_CMIB0
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#define PDL_INTC_VECTOR_OVI0 VECT_TMR0_OVI0
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#define PDL_INTC_VECTOR_CMIA1 VECT_TMR1_CMIA1
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#define PDL_INTC_VECTOR_CMIB1 VECT_TMR1_CMIB1
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#define PDL_INTC_VECTOR_OVI1 VECT_TMR1_OVI1
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#define PDL_INTC_VECTOR_CMIA2 VECT_TMR2_CMIA2
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#define PDL_INTC_VECTOR_CMIB2 VECT_TMR2_CMIB2
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#define PDL_INTC_VECTOR_OVI2 VECT_TMR2_OVI2
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#define PDL_INTC_VECTOR_CMIA3 VECT_TMR3_CMIA3
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#define PDL_INTC_VECTOR_CMIB3 VECT_TMR3_CMIB3
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#define PDL_INTC_VECTOR_OVI3 VECT_TMR3_OVI3
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#define PDL_INTC_VECTOR_DMAC0I VECT_DMAC_DMAC0I
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#define PDL_INTC_VECTOR_DMAC1I VECT_DMAC_DMAC1I
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#define PDL_INTC_VECTOR_DMAC2I VECT_DMAC_DMAC2I
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#define PDL_INTC_VECTOR_DMAC3I VECT_DMAC_DMAC3I
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#define PDL_INTC_VECTOR_EXDMAC0I VECT_EXDMAC_EXDMAC0I
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#define PDL_INTC_VECTOR_EXDMAC1I VECT_EXDMAC_EXDMAC1I
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#define PDL_INTC_VECTOR_ERI0 VECT_SCI0_ERI0
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#define PDL_INTC_VECTOR_RXI0 VECT_SCI0_RXI0
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#define PDL_INTC_VECTOR_TXI0 VECT_SCI0_TXI0
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#define PDL_INTC_VECTOR_TEI0 VECT_SCI0_TEI0
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#define PDL_INTC_VECTOR_ERI1 VECT_SCI1_ERI1
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#define PDL_INTC_VECTOR_RXI1 VECT_SCI1_RXI1
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#define PDL_INTC_VECTOR_TXI1 VECT_SCI1_TXI1
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#define PDL_INTC_VECTOR_TEI1 VECT_SCI1_TEI1
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#define PDL_INTC_VECTOR_ERI2 VECT_SCI2_ERI2
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#define PDL_INTC_VECTOR_RXI2 VECT_SCI2_RXI2
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#define PDL_INTC_VECTOR_TXI2 VECT_SCI2_TXI2
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#define PDL_INTC_VECTOR_TEI2 VECT_SCI2_TEI2
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#define PDL_INTC_VECTOR_ERI3 VECT_SCI3_ERI3
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#define PDL_INTC_VECTOR_RXI3 VECT_SCI3_RXI3
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#define PDL_INTC_VECTOR_TXI3 VECT_SCI3_TXI3
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#define PDL_INTC_VECTOR_TEI3 VECT_SCI3_TEI3
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#define PDL_INTC_VECTOR_ERI5 VECT_SCI5_ERI5
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#define PDL_INTC_VECTOR_RXI5 VECT_SCI5_RXI5
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#define PDL_INTC_VECTOR_TXI5 VECT_SCI5_TXI5
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#define PDL_INTC_VECTOR_TEI5 VECT_SCI5_TEI5
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#define PDL_INTC_VECTOR_ERI6 VECT_SCI6_ERI6
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#define PDL_INTC_VECTOR_RXI6 VECT_SCI6_RXI6
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#define PDL_INTC_VECTOR_TXI6 VECT_SCI6_TXI6
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#define PDL_INTC_VECTOR_TEI6 VECT_SCI6_TEI6
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#define PDL_INTC_VECTOR_ICEEI0 VECT_RIIC0_ICEEI0
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#define PDL_INTC_VECTOR_ICRXI0 VECT_RIIC0_ICRXI0
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#define PDL_INTC_VECTOR_ICTXI0 VECT_RIIC0_ICTXI0
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#define PDL_INTC_VECTOR_ICTEI0 VECT_RIIC0_ICTEI0
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#define PDL_INTC_VECTOR_ICEEI1 VECT_RIIC1_ICEEI1
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#define PDL_INTC_VECTOR_ICRXI1 VECT_RIIC1_ICRXI1
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#define PDL_INTC_VECTOR_ICTXI1 VECT_RIIC1_ICTXI1
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#define PDL_INTC_VECTOR_ICTEI1 VECT_RIIC1_ICTEI1
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#endif
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/* End of file */
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