124 lines
3.5 KiB
C
124 lines
3.5 KiB
C
/*""FILE COMMENT""*******************************************************
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* System Name : 12-bit ADC converter API for RX62Nxx
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* File Name : r_pdl_adc_12.h
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* Version : 1.02
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* Contents : ADC_12 function prototypes
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* Customer :
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* Model :
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* Order :
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* CPU : RX
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* Compiler : RXC
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* OS :
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* Programmer :
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* Note :
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************************************************************************
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* Copyright, 2011. Renesas Electronics Corporation
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* and Renesas Solutions Corporation
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************************************************************************
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* History : 2011.04.08
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* : Ver 1.02
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* : CS-5 release.
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*""FILE COMMENT END""**************************************************/
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#ifndef R_PDL_ADC_12_H
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#define R_PDL_ADC_12_H
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#include "r_pdl_common_defs_RX62Nxx.h"
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/* Function prototypes */
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bool R_ADC_12_Create(
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uint8_t,
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uint32_t,
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uint16_t,
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uint16_t,
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void *,
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uint8_t
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);
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bool R_ADC_12_Destroy(
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uint8_t
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);
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bool R_ADC_12_Control(
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uint8_t
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);
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bool R_ADC_12_Read(
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uint8_t,
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uint16_t *
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);
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/* Scan mode */
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#define PDL_ADC_12_SCAN_SINGLE 0x00000001ul
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#define PDL_ADC_12_SCAN_CONTINUOUS 0x00000002ul
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// Input channel selection
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#define PDL_ADC_12_CHANNEL_0 0x00000004ul
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#define PDL_ADC_12_CHANNEL_1 0x00000008ul
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#define PDL_ADC_12_CHANNEL_2 0x00000010ul
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#define PDL_ADC_12_CHANNEL_3 0x00000020ul
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#define PDL_ADC_12_CHANNEL_4 0x00000040ul
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#define PDL_ADC_12_CHANNEL_5 0x00000080ul
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#define PDL_ADC_12_CHANNEL_6 0x00000100ul
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#define PDL_ADC_12_CHANNEL_7 0x00000200ul
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/* Clock division */
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#define PDL_ADC_12_DIV_1 0x00000400ul
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#define PDL_ADC_12_DIV_2 0x00000800ul
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#define PDL_ADC_12_DIV_4 0x00001000ul
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#define PDL_ADC_12_DIV_8 0x00002000ul
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/* Data alignment */
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#define PDL_ADC_12_DATA_ALIGNMENT_LEFT 0x00004000ul
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#define PDL_ADC_12_DATA_ALIGNMENT_RIGHT 0x00008000ul
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/* Result register clearing */
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#define PDL_ADC_12_RETAIN_RESULT 0x00010000ul
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#define PDL_ADC_12_CLEAR_RESULT 0x00020000ul
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/* DMAC / DTC trigger control */
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#define PDL_ADC_12_DMAC_DTC_TRIGGER_DISABLE 0x00040000ul
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#define PDL_ADC_12_DMAC_TRIGGER_ENABLE 0x00080000ul
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#define PDL_ADC_12_DTC_TRIGGER_ENABLE 0x00100000ul
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/* Trigger selection */
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#define PDL_ADC_12_TRIGGER_SOFTWARE 0x0001u
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#define PDL_ADC_12_TRIGGER_ADTRG0 0x0002u
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#define PDL_ADC_12_TRIGGER_MTU0_ICCM_A 0x0004u
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#define PDL_ADC_12_TRIGGER_MTU0_ICCM_B 0x0008u
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#define PDL_ADC_12_TRIGGER_MTU0_MTU4_ICCM 0x0010u
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#define PDL_ADC_12_TRIGGER_MTU6_MTU10_ICCM 0x0020u
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#define PDL_ADC_12_TRIGGER_MTU0_CM_E 0x0040u
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#define PDL_ADC_12_TRIGGER_MTU0_CM_F 0x0080u
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#define PDL_ADC_12_TRIGGER_MTU4_CM 0x0100u
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#define PDL_ADC_12_TRIGGER_MTU10_CM 0x0200u
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#define PDL_ADC_12_TRIGGER_TMR0 0x0400u
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#define PDL_ADC_12_TRIGGER_TMR2 0x0800u
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/* Pin selection */
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#define PDL_ADC_12_PIN_ADTRG0_A 0x1000u
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#define PDL_ADC_12_PIN_ADTRG0_B 0x2000u
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/* Value addition mode selection */
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#define PDL_ADC_12_VALUE_ADD_CHANNEL_0 0x0001u
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#define PDL_ADC_12_VALUE_ADD_CHANNEL_1 0x0002u
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#define PDL_ADC_12_VALUE_ADD_CHANNEL_2 0x0004u
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#define PDL_ADC_12_VALUE_ADD_CHANNEL_3 0x0008u
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#define PDL_ADC_12_VALUE_ADD_CHANNEL_4 0x0010u
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#define PDL_ADC_12_VALUE_ADD_CHANNEL_5 0x0020u
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#define PDL_ADC_12_VALUE_ADD_CHANNEL_6 0x0040u
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#define PDL_ADC_12_VALUE_ADD_CHANNEL_7 0x0080u
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/* Value addition count selection */
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#define PDL_ADC_12_VALUE_ADD_TIME_1 0x0100u
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#define PDL_ADC_12_VALUE_ADD_TIME_2 0x0200u
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#define PDL_ADC_12_VALUE_ADD_TIME_3 0x0400u
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#define PDL_ADC_12_VALUE_ADD_TIME_4 0x0800u
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/* On / off control */
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#define PDL_ADC_12_0_ON 0x01u
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#define PDL_ADC_12_0_OFF 0x02u
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/* CPU control */
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#define PDL_ADC_12_CPU_OFF 0x04u
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#endif
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/* End of file */
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