92 lines
3.1 KiB
C
92 lines
3.1 KiB
C
/*
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* uffs/flash/nand.h
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*
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* COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Info:
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* Contains standard defines and IDs for NAND flash devices
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*/
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#ifndef __RTT_DFS_NAND_H__
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#define __RTT_DFS_NAND_H__
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/*
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* Standard NAND flash commands
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*/
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#define NAND_CMD_READ0 0 /* Read0 */
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#define NAND_CMD_READ1 1 /* Read1 */
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#define NAND_CMD_RNDOUT 5 /* Random data output */
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#define NAND_CMD_PAGEPROG 0x10 /* Write phase 2 */
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#define NAND_CMD_READOOB 0x50 /* Read oob */
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#define NAND_CMD_ERASE1 0x60 /* Erase phase 1 */
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#define NAND_CMD_STATUS 0x70 /* Status read */
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#define NAND_CMD_STATUS_MULTI 0x71
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#define NAND_CMD_SEQIN 0x80 /* Write phase 1 */
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#define NAND_CMD_RNDIN 0x85 /* Random data input */
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#define NAND_CMD_READID 0x90 /* ReadID,all-purpose command */
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#define NAND_CMD_ERASE2 0xd0 /* Erase phase 2 */
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#define NAND_CMD_RESET 0xff /* Reset */
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/* Extended commands for large page devices */
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#define NAND_CMD_READSTART 0x30
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#define NAND_CMD_RNDOUTSTART 0xE0
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#define NAND_CMD_CACHEDPROG 0x15
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#define NAND_CMD_READ_EDC 0x7b
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/* define low accessing value */
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#define TOTAL_BLOCKS 2048 /* total block of whole chip */
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#define PAGE_DATA_SIZE 2048 /* max size of page data */
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#define PAGE_SPARE_SIZE 64 /* max size of extended partition */
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#define PAGES_PER_BLOCK 64 /* max pages per block' */
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#define PAGE_SIZE (PAGE_DATA_SIZE+PAGE_SPARE_SIZE)/* max size per whole page */
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#define BLOCK_DATA_SIZE (PAGE_DATA_SIZE*PAGES_PER_BLOCK)/* max size per block' */
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/* bad flags offset in the oob area. */
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#define NAND_SMALL_BADBLOCK_POS 5 /* small page FLASH */
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#define NAND_LARGE_BADBLOCK_POS 0 /* large page FLASH */
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/* Option constants for bizarre disfunctionality and real
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* features
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*/
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/* Chip can not auto increment pages */
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#define NAND_NO_AUTOINCR 0x00000001
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/* Buswitdh is 16 bit */
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#define NAND_BUSWIDTH_16 0x00000002
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/* Device supports partial programming without padding */
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#define NAND_NO_PADDING 0x00000004
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/* Chip has cache program function */
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#define NAND_CACHEPRG 0x00000008
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/* Chip has copy back function */
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#define NAND_COPYBACK 0x00000010
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/* AND Chip which has 4 banks and a confusing page / block
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* assignment. See Renesas datasheet for further information */
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#define NAND_IS_AND 0x00000020
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/* Chip has a array of 4 pages which can be read without
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* additional ready /busy waits */
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#define NAND_4PAGE_ARRAY 0x00000040
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/* Options valid for Samsung large page devices */
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#define NAND_SAMSUNG_LP_OPTIONS \
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(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
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struct nand_flash_dev
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{
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char *name; /* chip name */
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int id; /* chip ID */
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unsigned long pagesize; /* max pages */
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unsigned long chipsize; /* size of whole chip iMB */
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unsigned long blocksize;/* size of block */
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unsigned long options; /* option */
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};
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struct nand_manufacturers
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{
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int id;
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char * name;
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};
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#endif /*__RTT_DFS_NAND_H__*/
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