342 lines
10 KiB
ArmAsm
342 lines
10 KiB
ArmAsm
/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Date Author Notes
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* 2020-01-15 bigmagic the first version
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* 2020-08-10 SummerGift support clang compiler
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* 2023-04-29 GuEe-GUI support kernel's ARM64 boot header
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*/
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#include "rtconfig.h"
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.section ".text.entrypoint","ax"
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#ifdef RT_USING_OFW
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/*
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* Our goal is to boot the rt-thread as possible without modifying the
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* bootloader's config, so we use the kernel's boot header for ARM64:
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* https://www.kernel.org/doc/html/latest/arm64/booting.html#call-the-kernel-image
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*/
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_head:
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b _start /* Executable code */
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.long 0 /* Executable code */
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.quad _text_offset /* Image load offset from start of RAM, little endian */
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.quad _end - _head /* Effective Image size, little endian (_end defined in link.lds) */
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.quad 0xa /* Kernel flags, little endian */
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.quad 0 /* Reserved */
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.quad 0 /* Reserved */
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.quad 0 /* Reserved */
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.ascii "ARM\x64" /* Magic number */
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.long 0 /* Reserved (used for PE COFF offset) */
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#endif
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/* Variable registers: x21~x28 */
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dtb_paddr .req x21
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boot_arg0 .req x22
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boot_arg1 .req x23
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boot_arg2 .req x24
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stack_top .req x25
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.global _start
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_start:
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/*
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* Boot CPU general-purpose register settings:
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* x0 = physical address of device tree blob (dtb) in system RAM.
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* x1 = 0 (reserved for future use)
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* x2 = 0 (reserved for future use)
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* x3 = 0 (reserved for future use)
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*/
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mov dtb_paddr, x0
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mov boot_arg0, x1
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mov boot_arg1, x2
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mov boot_arg2, x3
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#ifdef ARCH_ARM_BOOTWITH_FLUSH_CACHE
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bl __asm_flush_dcache_all
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#endif
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bl rt_hw_cpu_id_set
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/* read cpu id, stop slave cores */
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mrs x0, tpidr_el1
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cbz x0, .L__cpu_0 /* .L prefix is the local label in ELF */
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#ifndef RT_AMP_SLAVE
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/* cpu id > 0, stop */
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/* cpu id == 0 will also goto here after returned from entry() if possible */
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.L__current_cpu_idle:
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wfe
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b .L__current_cpu_idle
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#endif
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.L__cpu_0:
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/* set stack before our code, Define stack pointer for current exception level */
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adr x1, .el_stack_top
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/* set up EL1 */
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mrs x0, CurrentEL /* CurrentEL Register. bit 2, 3. Others reserved */
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and x0, x0, #12 /* clear reserved bits */
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/* running at EL3? */
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cmp x0, #12 /* 1100b. So, EL3 */
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bne .L__not_in_el3 /* 11? !EL3 -> 5: */
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/* should never be executed, just for completeness. (EL3) */
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mov x2, #0x5b1
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msr scr_el3, x2 /* SCR_ELn Secure Configuration Register */
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mov x2, #0x3c9
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msr spsr_el3, x2 /* SPSR_ELn. Saved Program Status Register. 1111001001 */
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adr x2, .L__not_in_el3
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msr elr_el3, x2
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eret /* Exception Return: from EL3, continue from .L__not_in_el3 */
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.L__not_in_el3: /* running at EL2 or EL1 */
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cmp x0, #4 /* 0x04 0100 EL1 */
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beq .L__in_el1 /* EL1 -> 5: */
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mrs x0, hcr_el2
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bic x0, x0, #0xff
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msr hcr_el2, x0
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msr sp_el1, x1 /* in EL2, set sp of EL1 to _start */
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/* enable CNTP for EL1 */
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mrs x0, cnthctl_el2 /* Counter-timer Hypervisor Control register */
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orr x0, x0, #3
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msr cnthctl_el2, x0
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msr cntvoff_el2, xzr
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/* enable AArch64 in EL1 */
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mov x0, #(1 << 31) /* AArch64 */
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orr x0, x0, #(1 << 1) /* SWIO hardwired on Pi3 */
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msr hcr_el2, x0
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mrs x0, hcr_el2
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/* change execution level to EL1 */
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mov x2, #0x3c4
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msr spsr_el2, x2 /* 1111000100 */
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adr x2, .L__in_el1
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msr elr_el2, x2
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eret /* exception return. from EL2. continue from .L__in_el1 */
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.macro GET_PHY reg, symbol
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adrp \reg, \symbol
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add \reg, \reg, #:lo12:\symbol
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.endm
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.L__in_el1:
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mov sp, x1 /* in EL1. Set sp to _start */
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/* Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction */
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mov x1, #0x00300000 /* Don't trap any SIMD/FP instructions in both EL0 and EL1 */
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msr cpacr_el1, x1
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/* applying context change */
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dsb ish
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isb
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/* clear bss */
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GET_PHY x1, __bss_start
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GET_PHY x2, __bss_end
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sub x2, x2, x1 /* get bss size */
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and x3, x2, #7 /* x3 is < 7 */
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ldr x4, =~0x7
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and x2, x2, x4 /* mask ~7 */
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.L__clean_bss_loop:
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cbz x2, .L__clean_bss_loop_1
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str xzr, [x1], #8
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sub x2, x2, #8
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b .L__clean_bss_loop
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.L__clean_bss_loop_1:
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cbz x3, .L__jump_to_entry
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strb wzr, [x1], #1
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sub x3, x3, #1
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b .L__clean_bss_loop_1
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.L__jump_to_entry: /* jump to C code, should not return */
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bl mmu_tcr_init
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bl get_ttbrn_base
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add x1, x0, #0x1000
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msr ttbr0_el1, x0
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msr ttbr1_el1, x1
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dsb sy
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#ifdef RT_USING_SMART
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ldr x2, =_start
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GET_PHY x3, _start
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sub x3, x3, x2
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#else
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mov x3,0
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#endif
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ldr x2, =0x10000000 /* map 256M memory for kernel space */
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bl rt_hw_mem_setup_early
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ldr x30, =after_mmu_enable /* set LR to after_mmu_enable function, it's a v_addr */
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mrs x1, sctlr_el1
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bic x1, x1, #(3 << 3) /* dis SA, SA0 */
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bic x1, x1, #(1 << 1) /* dis A */
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orr x1, x1, #(1 << 12) /* I */
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orr x1, x1, #(1 << 2) /* C */
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orr x1, x1, #(1 << 0) /* M */
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msr sctlr_el1, x1 /* enable MMU */
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dsb ish
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isb
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ic ialluis /* Invalidate all instruction caches in Inner Shareable domain to Point of Unification */
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dsb ish
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isb
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tlbi vmalle1 /* Invalidate all stage 1 translations used at EL1 with the current VMID */
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dsb ish
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isb
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ret
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after_mmu_enable:
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#ifdef RT_USING_SMART
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mrs x0, tcr_el1 /* disable ttbr0, only using kernel space */
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orr x0, x0, #(1 << 7)
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msr tcr_el1, x0
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msr ttbr0_el1, xzr
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dsb sy
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#endif
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mov x0, #1
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msr spsel, x0
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adr x1, .el_stack_top
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mov sp, x1 /* sp_el1 set to _start */
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b rtthread_startup
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#ifdef RT_USING_SMP
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/**
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* secondary cpu
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*/
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.global _secondary_cpu_entry
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_secondary_cpu_entry:
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bl rt_hw_cpu_id_set
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adr x1, .el_stack_top
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/* set up EL1 */
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mrs x0, CurrentEL /* CurrentEL Register. bit 2, 3. Others reserved */
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and x0, x0, #12 /* clear reserved bits */
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/* running at EL3? */
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cmp x0, #12 /* 1100b. So, EL3 */
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bne .L__not_in_el3_cpux /* 11? !EL3 -> 5: */
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/* should never be executed, just for completeness. (EL3) */
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mov x2, #0x5b1
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msr scr_el3, x2 /* SCR_ELn Secure Configuration Register */
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mov x2, #0x3c9
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msr spsr_el3, x2 /* SPSR_ELn. Saved Program Status Register. 1111001001 */
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adr x2, .L__not_in_el3_cpux
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msr elr_el3, x2
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eret /* Exception Return: from EL3, continue from .L__not_in_el3 */
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.L__not_in_el3_cpux: /* running at EL2 or EL1 */
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cmp x0, #4 /* 0x04 0100 EL1 */
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beq .L__in_el1_cpux /* EL1 -> 5: */
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mrs x0, hcr_el2
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bic x0, x0, #0xff
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msr hcr_el2, x0
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msr sp_el1, x1 /* in EL2, set sp of EL1 to _start */
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/* enable CNTP for EL1 */
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mrs x0, cnthctl_el2 /* Counter-timer Hypervisor Control register */
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orr x0, x0, #3
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msr cnthctl_el2, x0
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msr cntvoff_el2, xzr
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/* enable AArch64 in EL1 */
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mov x0, #(1 << 31) /* AArch64 */
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orr x0, x0, #(1 << 1) /* SWIO hardwired on Pi3 */
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msr hcr_el2, x0
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mrs x0, hcr_el2
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/* change execution level to EL1 */
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mov x2, #0x3c4
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msr spsr_el2, x2 /* 1111000100 */
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adr x2, .L__in_el1_cpux
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msr elr_el2, x2
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eret /* exception return. from EL2. continue from .L__in_el1 */
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.L__in_el1_cpux:
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mrs x0, tpidr_el1
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/* each cpu init stack is 8k */
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sub x1, x1, x0, lsl #13
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mov sp, x1 /* in EL1. Set sp to _start */
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/* Set CPACR_EL1 (Architecture Feature Access Control Register) to avoid trap from SIMD or float point instruction */
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mov x1, #0x00300000 /* Don't trap any SIMD/FP instructions in both EL0 and EL1 */
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msr cpacr_el1, x1
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.L__jump_to_entry_cpux: /* jump to C code, should not return */
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/* init mmu early */
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bl mmu_tcr_init
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bl get_ttbrn_base
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add x1, x0, #0x1000
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msr ttbr0_el1, x0
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msr ttbr1_el1, x1
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dsb sy
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ldr x30, =after_mmu_enable_cpux /* set LR to after_mmu_enable function, it's a v_addr */
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mrs x1, sctlr_el1
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bic x1, x1, #(3 << 3) /* dis SA, SA0 */
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bic x1, x1, #(1 << 1) /* dis A */
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orr x1, x1, #(1 << 12) /* I */
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orr x1, x1, #(1 << 2) /* C */
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orr x1, x1, #(1 << 0) /* M */
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msr sctlr_el1, x1 /* enable MMU */
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dsb sy
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isb sy
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ic ialluis /* Invalidate all instruction caches in Inner Shareable domain to Point of Unification */
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dsb sy
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isb sy
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tlbi vmalle1 /* Invalidate all stage 1 translations used at EL1 with the current VMID */
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dsb sy
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isb sy
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ret
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after_mmu_enable_cpux:
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#ifdef RT_USING_SMART
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mrs x0, tcr_el1 /* disable ttbr0, only using kernel space */
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orr x0, x0, #(1 << 7)
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msr tcr_el1, x0
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msr ttbr0_el1, xzr
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dsb sy
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#endif
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mov x0, #1
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msr spsel, x0
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mrs x0, tpidr_el1
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/* each cpu init stack is 8k */
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adr x1, .el_stack_top
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sub x1, x1, x0, lsl #13
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mov sp, x1 /* in EL1. Set sp to _start */
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b rt_hw_secondary_cpu_bsp_start
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#endif
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#ifndef RT_CPUS_NR
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#define RT_CPUS_NR 1
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#endif
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.align 12
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.el_stack:
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.space (8192 * RT_CPUS_NR)
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.el_stack_top:
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