709 lines
23 KiB
C
709 lines
23 KiB
C
/*
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* Copyright (c) 2021-2023 HPMicro
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef HPM_SOC_H
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#define HPM_SOC_H
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/* List of external IRQs */
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#define IRQn_GPIO0_A 1 /* GPIO0_A IRQ */
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#define IRQn_GPIO0_B 2 /* GPIO0_B IRQ */
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#define IRQn_GPIO0_C 3 /* GPIO0_C IRQ */
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#define IRQn_GPIO0_D 4 /* GPIO0_D IRQ */
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#define IRQn_GPIO0_X 5 /* GPIO0_X IRQ */
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#define IRQn_GPIO0_Y 6 /* GPIO0_Y IRQ */
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#define IRQn_GPIO0_Z 7 /* GPIO0_Z IRQ */
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#define IRQn_GPIO1_A 8 /* GPIO1_A IRQ */
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#define IRQn_GPIO1_B 9 /* GPIO1_B IRQ */
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#define IRQn_GPIO1_C 10 /* GPIO1_C IRQ */
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#define IRQn_GPIO1_D 11 /* GPIO1_D IRQ */
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#define IRQn_GPIO1_X 12 /* GPIO1_X IRQ */
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#define IRQn_GPIO1_Y 13 /* GPIO1_Y IRQ */
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#define IRQn_GPIO1_Z 14 /* GPIO1_Z IRQ */
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#define IRQn_ADC0 15 /* ADC0 IRQ */
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#define IRQn_ADC1 16 /* ADC1 IRQ */
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#define IRQn_ADC2 17 /* ADC2 IRQ */
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#define IRQn_SDFM 18 /* SDFM IRQ */
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#define IRQn_DAC0 19 /* DAC0 IRQ */
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#define IRQn_DAC1 20 /* DAC1 IRQ */
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#define IRQn_ACMP_0 21 /* ACMP[0] IRQ */
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#define IRQn_ACMP_1 22 /* ACMP[1] IRQ */
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#define IRQn_ACMP_2 23 /* ACMP[2] IRQ */
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#define IRQn_ACMP_3 24 /* ACMP[3] IRQ */
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#define IRQn_SPI0 25 /* SPI0 IRQ */
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#define IRQn_SPI1 26 /* SPI1 IRQ */
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#define IRQn_SPI2 27 /* SPI2 IRQ */
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#define IRQn_SPI3 28 /* SPI3 IRQ */
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#define IRQn_UART0 29 /* UART0 IRQ */
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#define IRQn_UART1 30 /* UART1 IRQ */
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#define IRQn_UART2 31 /* UART2 IRQ */
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#define IRQn_UART3 32 /* UART3 IRQ */
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#define IRQn_UART4 33 /* UART4 IRQ */
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#define IRQn_UART5 34 /* UART5 IRQ */
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#define IRQn_UART6 35 /* UART6 IRQ */
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#define IRQn_UART7 36 /* UART7 IRQ */
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#define IRQn_CAN0 37 /* CAN0 IRQ */
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#define IRQn_CAN1 38 /* CAN1 IRQ */
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#define IRQn_CAN2 39 /* CAN2 IRQ */
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#define IRQn_CAN3 40 /* CAN3 IRQ */
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#define IRQn_PTPC 41 /* PTPC IRQ */
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#define IRQn_WDG0 42 /* WDG0 IRQ */
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#define IRQn_WDG1 43 /* WDG1 IRQ */
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#define IRQn_TSNS 44 /* TSNS IRQ */
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#define IRQn_MBX0A 45 /* MBX0A IRQ */
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#define IRQn_MBX0B 46 /* MBX0B IRQ */
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#define IRQn_MBX1A 47 /* MBX1A IRQ */
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#define IRQn_MBX1B 48 /* MBX1B IRQ */
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#define IRQn_GPTMR0 49 /* GPTMR0 IRQ */
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#define IRQn_GPTMR1 50 /* GPTMR1 IRQ */
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#define IRQn_GPTMR2 51 /* GPTMR2 IRQ */
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#define IRQn_GPTMR3 52 /* GPTMR3 IRQ */
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#define IRQn_I2C0 53 /* I2C0 IRQ */
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#define IRQn_I2C1 54 /* I2C1 IRQ */
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#define IRQn_I2C2 55 /* I2C2 IRQ */
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#define IRQn_I2C3 56 /* I2C3 IRQ */
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#define IRQn_PWM0 57 /* PWM0 IRQ */
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#define IRQn_HALL0 58 /* HALL0 IRQ */
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#define IRQn_QEI0 59 /* QEI0 IRQ */
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#define IRQn_PWM1 60 /* PWM1 IRQ */
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#define IRQn_HALL1 61 /* HALL1 IRQ */
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#define IRQn_QEI1 62 /* QEI1 IRQ */
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#define IRQn_PWM2 63 /* PWM2 IRQ */
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#define IRQn_HALL2 64 /* HALL2 IRQ */
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#define IRQn_QEI2 65 /* QEI2 IRQ */
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#define IRQn_PWM3 66 /* PWM3 IRQ */
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#define IRQn_HALL3 67 /* HALL3 IRQ */
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#define IRQn_QEI3 68 /* QEI3 IRQ */
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#define IRQn_SDP 69 /* SDP IRQ */
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#define IRQn_XPI0 70 /* XPI0 IRQ */
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#define IRQn_XDMA 71 /* XDMA IRQ */
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#define IRQn_HDMA 72 /* HDMA IRQ */
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#define IRQn_RNG 73 /* RNG IRQ */
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#define IRQn_USB0 74 /* USB0 IRQ */
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#define IRQn_PSEC 75 /* PSEC IRQ */
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#define IRQn_PGPIO 76 /* PGPIO IRQ */
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#define IRQn_PWDG 77 /* PWDG IRQ */
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#define IRQn_PTMR 78 /* PTMR IRQ */
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#define IRQn_PUART 79 /* PUART IRQ */
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#define IRQn_FUSE 80 /* FUSE IRQ */
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#define IRQn_SECMON 81 /* SECMON IRQ */
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#define IRQn_RTC 82 /* RTC IRQ */
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#define IRQn_BUTN 83 /* BUTN IRQ */
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#define IRQn_BGPIO 84 /* BGPIO IRQ */
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#define IRQn_BVIO 85 /* BVIO IRQ */
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#define IRQn_BROWNOUT 86 /* BROWNOUT IRQ */
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#define IRQn_SYSCTL 87 /* SYSCTL IRQ */
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#define IRQn_DEBUG_0 88 /* DEBUG[0] IRQ */
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#define IRQn_DEBUG_1 89 /* DEBUG[1] IRQ */
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#define IRQn_LIN0 90 /* LIN0 IRQ */
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#define IRQn_LIN1 91 /* LIN1 IRQ */
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#define IRQn_LIN2 92 /* LIN2 IRQ */
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#define IRQn_LIN3 93 /* LIN3 IRQ */
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#include "hpm_common.h"
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#include "hpm_gpio_regs.h"
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/* Address of GPIO instances */
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/* FGPIO base address */
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#define HPM_FGPIO_BASE (0xC0000UL)
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/* FGPIO base pointer */
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#define HPM_FGPIO ((GPIO_Type *) HPM_FGPIO_BASE)
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/* GPIO0 base address */
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#define HPM_GPIO0_BASE (0xF0000000UL)
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/* GPIO0 base pointer */
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#define HPM_GPIO0 ((GPIO_Type *) HPM_GPIO0_BASE)
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/* GPIO1 base address */
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#define HPM_GPIO1_BASE (0xF0004000UL)
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/* GPIO1 base pointer */
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#define HPM_GPIO1 ((GPIO_Type *) HPM_GPIO1_BASE)
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/* PGPIO base address */
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#define HPM_PGPIO_BASE (0xF40DC000UL)
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/* PGPIO base pointer */
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#define HPM_PGPIO ((GPIO_Type *) HPM_PGPIO_BASE)
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/* BGPIO base address */
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#define HPM_BGPIO_BASE (0xF5014000UL)
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/* BGPIO base pointer */
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#define HPM_BGPIO ((GPIO_Type *) HPM_BGPIO_BASE)
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/* Address of DM instances */
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/* DM base address */
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#define HPM_DM_BASE (0x30000000UL)
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/* Address of XBUS_SOC instances */
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/* GPV_SOC base address */
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#define HPM_GPV_SOC_BASE (0x30100000UL)
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#include "hpm_plic_regs.h"
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/* Address of PLIC instances */
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/* PLIC base address */
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#define HPM_PLIC_BASE (0xE4000000UL)
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/* PLIC base pointer */
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#define HPM_PLIC ((PLIC_Type *) HPM_PLIC_BASE)
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#include "hpm_mchtmr_regs.h"
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/* Address of MCHTMR instances */
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/* MCHTMR base address */
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#define HPM_MCHTMR_BASE (0xE6000000UL)
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/* MCHTMR base pointer */
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#define HPM_MCHTMR ((MCHTMR_Type *) HPM_MCHTMR_BASE)
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#include "hpm_plic_sw_regs.h"
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/* Address of PLICSW instances */
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/* PLICSW base address */
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#define HPM_PLICSW_BASE (0xE6400000UL)
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/* PLICSW base pointer */
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#define HPM_PLICSW ((PLIC_SW_Type *) HPM_PLICSW_BASE)
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#include "hpm_gpiom_regs.h"
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/* Address of GPIOM instances */
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/* GPIOM base address */
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#define HPM_GPIOM_BASE (0xF0008000UL)
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/* GPIOM base pointer */
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#define HPM_GPIOM ((GPIOM_Type *) HPM_GPIOM_BASE)
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#include "hpm_adc16_regs.h"
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/* Address of ADC16 instances */
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/* ADC0 base address */
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#define HPM_ADC0_BASE (0xF0010000UL)
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/* ADC0 base pointer */
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#define HPM_ADC0 ((ADC16_Type *) HPM_ADC0_BASE)
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/* ADC1 base address */
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#define HPM_ADC1_BASE (0xF0014000UL)
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/* ADC1 base pointer */
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#define HPM_ADC1 ((ADC16_Type *) HPM_ADC1_BASE)
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/* ADC2 base address */
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#define HPM_ADC2_BASE (0xF0018000UL)
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/* ADC2 base pointer */
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#define HPM_ADC2 ((ADC16_Type *) HPM_ADC2_BASE)
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#include "hpm_sdm_regs.h"
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/* Address of SDM instances */
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/* SDM base address */
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#define HPM_SDM_BASE (0xF001C000UL)
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/* SDM base pointer */
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#define HPM_SDM ((SDM_Type *) HPM_SDM_BASE)
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#include "hpm_acmp_regs.h"
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/* Address of ACMP instances */
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/* ACMP base address */
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#define HPM_ACMP_BASE (0xF0020000UL)
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/* ACMP base pointer */
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#define HPM_ACMP ((ACMP_Type *) HPM_ACMP_BASE)
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#include "hpm_dac_regs.h"
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/* Address of DAC instances */
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/* DAC0 base address */
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#define HPM_DAC0_BASE (0xF0024000UL)
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/* DAC0 base pointer */
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#define HPM_DAC0 ((DAC_Type *) HPM_DAC0_BASE)
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/* DAC1 base address */
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#define HPM_DAC1_BASE (0xF0028000UL)
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/* DAC1 base pointer */
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#define HPM_DAC1 ((DAC_Type *) HPM_DAC1_BASE)
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#include "hpm_spi_regs.h"
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/* Address of SPI instances */
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/* SPI0 base address */
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#define HPM_SPI0_BASE (0xF0030000UL)
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/* SPI0 base pointer */
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#define HPM_SPI0 ((SPI_Type *) HPM_SPI0_BASE)
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/* SPI1 base address */
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#define HPM_SPI1_BASE (0xF0034000UL)
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/* SPI1 base pointer */
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#define HPM_SPI1 ((SPI_Type *) HPM_SPI1_BASE)
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/* SPI2 base address */
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#define HPM_SPI2_BASE (0xF0038000UL)
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/* SPI2 base pointer */
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#define HPM_SPI2 ((SPI_Type *) HPM_SPI2_BASE)
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/* SPI3 base address */
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#define HPM_SPI3_BASE (0xF003C000UL)
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/* SPI3 base pointer */
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#define HPM_SPI3 ((SPI_Type *) HPM_SPI3_BASE)
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#include "hpm_uart_regs.h"
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/* Address of UART instances */
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/* UART0 base address */
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#define HPM_UART0_BASE (0xF0040000UL)
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/* UART0 base pointer */
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#define HPM_UART0 ((UART_Type *) HPM_UART0_BASE)
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/* UART1 base address */
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#define HPM_UART1_BASE (0xF0044000UL)
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/* UART1 base pointer */
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#define HPM_UART1 ((UART_Type *) HPM_UART1_BASE)
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/* UART2 base address */
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#define HPM_UART2_BASE (0xF0048000UL)
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/* UART2 base pointer */
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#define HPM_UART2 ((UART_Type *) HPM_UART2_BASE)
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/* UART3 base address */
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#define HPM_UART3_BASE (0xF004C000UL)
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/* UART3 base pointer */
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#define HPM_UART3 ((UART_Type *) HPM_UART3_BASE)
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/* UART4 base address */
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#define HPM_UART4_BASE (0xF0050000UL)
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/* UART4 base pointer */
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#define HPM_UART4 ((UART_Type *) HPM_UART4_BASE)
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/* UART5 base address */
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#define HPM_UART5_BASE (0xF0054000UL)
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/* UART5 base pointer */
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#define HPM_UART5 ((UART_Type *) HPM_UART5_BASE)
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/* UART6 base address */
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#define HPM_UART6_BASE (0xF0058000UL)
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/* UART6 base pointer */
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#define HPM_UART6 ((UART_Type *) HPM_UART6_BASE)
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/* UART7 base address */
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#define HPM_UART7_BASE (0xF005C000UL)
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/* UART7 base pointer */
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#define HPM_UART7 ((UART_Type *) HPM_UART7_BASE)
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/* PUART base address */
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#define HPM_PUART_BASE (0xF40E4000UL)
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/* PUART base pointer */
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#define HPM_PUART ((UART_Type *) HPM_PUART_BASE)
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#include "hpm_mcan_regs.h"
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/* Address of MCAN instances */
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/* MCAN0 base address */
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#define HPM_MCAN0_BASE (0xF0080000UL)
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/* MCAN0 base pointer */
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#define HPM_MCAN0 ((MCAN_Type *) HPM_MCAN0_BASE)
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/* MCAN1 base address */
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#define HPM_MCAN1_BASE (0xF0084000UL)
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/* MCAN1 base pointer */
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#define HPM_MCAN1 ((MCAN_Type *) HPM_MCAN1_BASE)
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/* MCAN2 base address */
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#define HPM_MCAN2_BASE (0xF0088000UL)
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/* MCAN2 base pointer */
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#define HPM_MCAN2 ((MCAN_Type *) HPM_MCAN2_BASE)
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/* MCAN3 base address */
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#define HPM_MCAN3_BASE (0xF008C000UL)
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/* MCAN3 base pointer */
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#define HPM_MCAN3 ((MCAN_Type *) HPM_MCAN3_BASE)
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#include "hpm_wdg_regs.h"
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/* Address of WDOG instances */
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/* WDG0 base address */
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#define HPM_WDG0_BASE (0xF0090000UL)
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/* WDG0 base pointer */
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#define HPM_WDG0 ((WDG_Type *) HPM_WDG0_BASE)
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/* WDG1 base address */
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#define HPM_WDG1_BASE (0xF0094000UL)
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/* WDG1 base pointer */
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#define HPM_WDG1 ((WDG_Type *) HPM_WDG1_BASE)
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/* PWDG base address */
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#define HPM_PWDG_BASE (0xF40E8000UL)
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/* PWDG base pointer */
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#define HPM_PWDG ((WDG_Type *) HPM_PWDG_BASE)
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#include "hpm_mbx_regs.h"
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/* Address of MBX instances */
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/* MBX0A base address */
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#define HPM_MBX0A_BASE (0xF00A0000UL)
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/* MBX0A base pointer */
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#define HPM_MBX0A ((MBX_Type *) HPM_MBX0A_BASE)
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/* MBX0B base address */
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#define HPM_MBX0B_BASE (0xF00A4000UL)
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/* MBX0B base pointer */
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#define HPM_MBX0B ((MBX_Type *) HPM_MBX0B_BASE)
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/* MBX1A base address */
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#define HPM_MBX1A_BASE (0xF00A8000UL)
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/* MBX1A base pointer */
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#define HPM_MBX1A ((MBX_Type *) HPM_MBX1A_BASE)
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/* MBX1B base address */
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#define HPM_MBX1B_BASE (0xF00AC000UL)
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/* MBX1B base pointer */
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#define HPM_MBX1B ((MBX_Type *) HPM_MBX1B_BASE)
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#include "hpm_ptpc_regs.h"
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/* Address of PTPC instances */
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/* PTPC base address */
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#define HPM_PTPC_BASE (0xF00B0000UL)
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/* PTPC base pointer */
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#define HPM_PTPC ((PTPC_Type *) HPM_PTPC_BASE)
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#include "hpm_crc_regs.h"
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/* Address of CRC instances */
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/* CRC base address */
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#define HPM_CRC_BASE (0xF00B8000UL)
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/* CRC base pointer */
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#define HPM_CRC ((CRC_Type *) HPM_CRC_BASE)
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#include "hpm_dmamux_regs.h"
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/* Address of DMAMUX instances */
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/* DMAMUX base address */
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#define HPM_DMAMUX_BASE (0xF00C0000UL)
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/* DMAMUX base pointer */
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#define HPM_DMAMUX ((DMAMUX_Type *) HPM_DMAMUX_BASE)
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#include "hpm_dma_regs.h"
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/* Address of DMA instances */
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/* HDMA base address */
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#define HPM_HDMA_BASE (0xF00C4000UL)
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/* HDMA base pointer */
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#define HPM_HDMA ((DMA_Type *) HPM_HDMA_BASE)
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/* XDMA base address */
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#define HPM_XDMA_BASE (0xF3048000UL)
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/* XDMA base pointer */
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#define HPM_XDMA ((DMA_Type *) HPM_XDMA_BASE)
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#include "hpm_rng_regs.h"
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/* Address of RNG instances */
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/* RNG base address */
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#define HPM_RNG_BASE (0xF00C8000UL)
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/* RNG base pointer */
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#define HPM_RNG ((RNG_Type *) HPM_RNG_BASE)
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#include "hpm_keym_regs.h"
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/* Address of KEYM instances */
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/* KEYM base address */
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#define HPM_KEYM_BASE (0xF00CC000UL)
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/* KEYM base pointer */
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#define HPM_KEYM ((KEYM_Type *) HPM_KEYM_BASE)
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#include "hpm_pwm_regs.h"
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/* Address of PWM instances */
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/* PWM0 base address */
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#define HPM_PWM0_BASE (0xF0200000UL)
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/* PWM0 base pointer */
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#define HPM_PWM0 ((PWM_Type *) HPM_PWM0_BASE)
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/* PWM1 base address */
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#define HPM_PWM1_BASE (0xF0210000UL)
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/* PWM1 base pointer */
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#define HPM_PWM1 ((PWM_Type *) HPM_PWM1_BASE)
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/* PWM2 base address */
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#define HPM_PWM2_BASE (0xF0220000UL)
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/* PWM2 base pointer */
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#define HPM_PWM2 ((PWM_Type *) HPM_PWM2_BASE)
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/* PWM3 base address */
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#define HPM_PWM3_BASE (0xF0230000UL)
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/* PWM3 base pointer */
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#define HPM_PWM3 ((PWM_Type *) HPM_PWM3_BASE)
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#include "hpm_hall_regs.h"
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/* Address of HALL instances */
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/* HALL0 base address */
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#define HPM_HALL0_BASE (0xF0204000UL)
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/* HALL0 base pointer */
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#define HPM_HALL0 ((HALL_Type *) HPM_HALL0_BASE)
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/* HALL1 base address */
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#define HPM_HALL1_BASE (0xF0214000UL)
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/* HALL1 base pointer */
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#define HPM_HALL1 ((HALL_Type *) HPM_HALL1_BASE)
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/* HALL2 base address */
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#define HPM_HALL2_BASE (0xF0224000UL)
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/* HALL2 base pointer */
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#define HPM_HALL2 ((HALL_Type *) HPM_HALL2_BASE)
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/* HALL3 base address */
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#define HPM_HALL3_BASE (0xF0234000UL)
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/* HALL3 base pointer */
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#define HPM_HALL3 ((HALL_Type *) HPM_HALL3_BASE)
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#include "hpm_qei_regs.h"
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/* Address of QEI instances */
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/* QEI0 base address */
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#define HPM_QEI0_BASE (0xF0208000UL)
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/* QEI0 base pointer */
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#define HPM_QEI0 ((QEI_Type *) HPM_QEI0_BASE)
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/* QEI1 base address */
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#define HPM_QEI1_BASE (0xF0218000UL)
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/* QEI1 base pointer */
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#define HPM_QEI1 ((QEI_Type *) HPM_QEI1_BASE)
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/* QEI2 base address */
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#define HPM_QEI2_BASE (0xF0228000UL)
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/* QEI2 base pointer */
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#define HPM_QEI2 ((QEI_Type *) HPM_QEI2_BASE)
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/* QEI3 base address */
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#define HPM_QEI3_BASE (0xF0238000UL)
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/* QEI3 base pointer */
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#define HPM_QEI3 ((QEI_Type *) HPM_QEI3_BASE)
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#include "hpm_trgm_regs.h"
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/* Address of TRGM instances */
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/* TRGM0 base address */
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#define HPM_TRGM0_BASE (0xF020C000UL)
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/* TRGM0 base pointer */
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#define HPM_TRGM0 ((TRGM_Type *) HPM_TRGM0_BASE)
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/* TRGM1 base address */
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#define HPM_TRGM1_BASE (0xF021C000UL)
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/* TRGM1 base pointer */
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#define HPM_TRGM1 ((TRGM_Type *) HPM_TRGM1_BASE)
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/* TRGM2 base address */
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#define HPM_TRGM2_BASE (0xF022C000UL)
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/* TRGM2 base pointer */
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#define HPM_TRGM2 ((TRGM_Type *) HPM_TRGM2_BASE)
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/* TRGM3 base address */
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#define HPM_TRGM3_BASE (0xF023C000UL)
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/* TRGM3 base pointer */
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#define HPM_TRGM3 ((TRGM_Type *) HPM_TRGM3_BASE)
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#include "hpm_pla_regs.h"
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/* Address of PLA instances */
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/* PLA0 base address */
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#define HPM_PLA0_BASE (0xF020E000UL)
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/* PLA0 base pointer */
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#define HPM_PLA0 ((PLA_Type *) HPM_PLA0_BASE)
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/* PLA1 base address */
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#define HPM_PLA1_BASE (0xF021E000UL)
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/* PLA1 base pointer */
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#define HPM_PLA1 ((PLA_Type *) HPM_PLA1_BASE)
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#include "hpm_synt_regs.h"
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/* Address of SYNT instances */
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/* SYNT base address */
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#define HPM_SYNT_BASE (0xF0240000UL)
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/* SYNT base pointer */
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#define HPM_SYNT ((SYNT_Type *) HPM_SYNT_BASE)
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/* Address of PLA_X2 instances */
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/* PLA_X2 base address */
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#define HPM_PLA_X2_BASE (0xF024E000UL)
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#include "hpm_usb_regs.h"
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/* Address of USB instances */
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/* USB0 base address */
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#define HPM_USB0_BASE (0xF2020000UL)
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/* USB0 base pointer */
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#define HPM_USB0 ((USB_Type *) HPM_USB0_BASE)
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#include "hpm_gptmr_regs.h"
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/* Address of TMR instances */
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/* GPTMR0 base address */
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#define HPM_GPTMR0_BASE (0xF3000000UL)
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/* GPTMR0 base pointer */
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#define HPM_GPTMR0 ((GPTMR_Type *) HPM_GPTMR0_BASE)
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/* GPTMR1 base address */
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#define HPM_GPTMR1_BASE (0xF3004000UL)
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/* GPTMR1 base pointer */
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#define HPM_GPTMR1 ((GPTMR_Type *) HPM_GPTMR1_BASE)
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/* GPTMR2 base address */
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#define HPM_GPTMR2_BASE (0xF3008000UL)
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/* GPTMR2 base pointer */
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#define HPM_GPTMR2 ((GPTMR_Type *) HPM_GPTMR2_BASE)
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/* GPTMR3 base address */
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#define HPM_GPTMR3_BASE (0xF300C000UL)
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/* GPTMR3 base pointer */
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#define HPM_GPTMR3 ((GPTMR_Type *) HPM_GPTMR3_BASE)
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/* PTMR base address */
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#define HPM_PTMR_BASE (0xF40E0000UL)
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/* PTMR base pointer */
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#define HPM_PTMR ((GPTMR_Type *) HPM_PTMR_BASE)
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#include "hpm_i2c_regs.h"
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/* Address of I2C instances */
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/* I2C0 base address */
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#define HPM_I2C0_BASE (0xF3020000UL)
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/* I2C0 base pointer */
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#define HPM_I2C0 ((I2C_Type *) HPM_I2C0_BASE)
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/* I2C1 base address */
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#define HPM_I2C1_BASE (0xF3024000UL)
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/* I2C1 base pointer */
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#define HPM_I2C1 ((I2C_Type *) HPM_I2C1_BASE)
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/* I2C2 base address */
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#define HPM_I2C2_BASE (0xF3028000UL)
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/* I2C2 base pointer */
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#define HPM_I2C2 ((I2C_Type *) HPM_I2C2_BASE)
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/* I2C3 base address */
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#define HPM_I2C3_BASE (0xF302C000UL)
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/* I2C3 base pointer */
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#define HPM_I2C3 ((I2C_Type *) HPM_I2C3_BASE)
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#include "hpm_lin_regs.h"
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/* Address of LIN instances */
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/* LIN0 base address */
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#define HPM_LIN0_BASE (0xF3030000UL)
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/* LIN0 base pointer */
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#define HPM_LIN0 ((LIN_Type *) HPM_LIN0_BASE)
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/* LIN1 base address */
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#define HPM_LIN1_BASE (0xF3034000UL)
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/* LIN1 base pointer */
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#define HPM_LIN1 ((LIN_Type *) HPM_LIN1_BASE)
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/* LIN2 base address */
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#define HPM_LIN2_BASE (0xF3038000UL)
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/* LIN2 base pointer */
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#define HPM_LIN2 ((LIN_Type *) HPM_LIN2_BASE)
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/* LIN3 base address */
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#define HPM_LIN3_BASE (0xF303C000UL)
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/* LIN3 base pointer */
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#define HPM_LIN3 ((LIN_Type *) HPM_LIN3_BASE)
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#include "hpm_sdp_regs.h"
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/* Address of SDP instances */
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/* SDP base address */
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#define HPM_SDP_BASE (0xF304C000UL)
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/* SDP base pointer */
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#define HPM_SDP ((SDP_Type *) HPM_SDP_BASE)
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/* Address of ROMC instances */
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/* ROMC base address */
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#define HPM_ROMC_BASE (0xF3054000UL)
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#include "hpm_sysctl_regs.h"
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/* Address of SYSCTL instances */
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/* SYSCTL base address */
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#define HPM_SYSCTL_BASE (0xF4000000UL)
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/* SYSCTL base pointer */
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#define HPM_SYSCTL ((SYSCTL_Type *) HPM_SYSCTL_BASE)
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#include "hpm_ioc_regs.h"
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/* Address of IOC instances */
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/* IOC base address */
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#define HPM_IOC_BASE (0xF4040000UL)
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/* IOC base pointer */
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#define HPM_IOC ((IOC_Type *) HPM_IOC_BASE)
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/* PIOC base address */
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#define HPM_PIOC_BASE (0xF40D8000UL)
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/* PIOC base pointer */
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#define HPM_PIOC ((IOC_Type *) HPM_PIOC_BASE)
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/* BIOC base address */
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#define HPM_BIOC_BASE (0xF5010000UL)
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/* BIOC base pointer */
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#define HPM_BIOC ((IOC_Type *) HPM_BIOC_BASE)
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#include "hpm_otp_regs.h"
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/* Address of OTP instances */
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/* OTPSHW base address */
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#define HPM_OTPSHW_BASE (0xF4080000UL)
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/* OTPSHW base pointer */
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#define HPM_OTPSHW ((OTP_Type *) HPM_OTPSHW_BASE)
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/* OTP base address */
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#define HPM_OTP_BASE (0xF40C8000UL)
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/* OTP base pointer */
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#define HPM_OTP ((OTP_Type *) HPM_OTP_BASE)
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#include "hpm_ppor_regs.h"
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/* Address of PPOR instances */
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/* PPOR base address */
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#define HPM_PPOR_BASE (0xF40C0000UL)
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/* PPOR base pointer */
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#define HPM_PPOR ((PPOR_Type *) HPM_PPOR_BASE)
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#include "hpm_pcfg_regs.h"
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/* Address of PCFG instances */
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/* PCFG base address */
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#define HPM_PCFG_BASE (0xF40C4000UL)
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/* PCFG base pointer */
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#define HPM_PCFG ((PCFG_Type *) HPM_PCFG_BASE)
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#include "hpm_psec_regs.h"
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/* Address of PSEC instances */
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/* PSEC base address */
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#define HPM_PSEC_BASE (0xF40CC000UL)
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/* PSEC base pointer */
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#define HPM_PSEC ((PSEC_Type *) HPM_PSEC_BASE)
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#include "hpm_pmon_regs.h"
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/* Address of PMON instances */
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/* PMON base address */
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#define HPM_PMON_BASE (0xF40D0000UL)
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/* PMON base pointer */
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#define HPM_PMON ((PMON_Type *) HPM_PMON_BASE)
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#include "hpm_pgpr_regs.h"
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/* Address of PGPR instances */
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/* PGPR base address */
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#define HPM_PGPR_BASE (0xF40D4000UL)
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/* PGPR base pointer */
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#define HPM_PGPR ((PGPR_Type *) HPM_PGPR_BASE)
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#include "hpm_pllctlv2_regs.h"
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/* Address of PLLCTLV2 instances */
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/* PLLCTLV2 base address */
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#define HPM_PLLCTLV2_BASE (0xF4100000UL)
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/* PLLCTLV2 base pointer */
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#define HPM_PLLCTLV2 ((PLLCTLV2_Type *) HPM_PLLCTLV2_BASE)
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#include "hpm_tsns_regs.h"
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/* Address of TSNS instances */
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/* TSNS base address */
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#define HPM_TSNS_BASE (0xF4104000UL)
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/* TSNS base pointer */
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#define HPM_TSNS ((TSNS_Type *) HPM_TSNS_BASE)
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/* Address of BACC instances */
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/* BACC base address */
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#define HPM_BACC_BASE (0xF5000000UL)
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#include "hpm_bpor_regs.h"
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/* Address of BPOR instances */
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/* BPOR base address */
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#define HPM_BPOR_BASE (0xF5004000UL)
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/* BPOR base pointer */
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#define HPM_BPOR ((BPOR_Type *) HPM_BPOR_BASE)
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#include "hpm_bcfg_regs.h"
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/* Address of BCFG instances */
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/* BCFG base address */
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#define HPM_BCFG_BASE (0xF5008000UL)
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/* BCFG base pointer */
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#define HPM_BCFG ((BCFG_Type *) HPM_BCFG_BASE)
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#include "hpm_butn_regs.h"
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/* Address of BUTN instances */
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/* BUTN base address */
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#define HPM_BUTN_BASE (0xF500C000UL)
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/* BUTN base pointer */
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#define HPM_BUTN ((BUTN_Type *) HPM_BUTN_BASE)
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#include "hpm_bgpr_regs.h"
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/* Address of BGPR instances */
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/* BGPR base address */
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#define HPM_BGPR_BASE (0xF5018000UL)
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/* BGPR base pointer */
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#define HPM_BGPR ((BGPR_Type *) HPM_BGPR_BASE)
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#include "hpm_bsec_regs.h"
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/* Address of BSEC instances */
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/* BSEC base address */
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#define HPM_BSEC_BASE (0xF5040000UL)
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/* BSEC base pointer */
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#define HPM_BSEC ((BSEC_Type *) HPM_BSEC_BASE)
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#include "hpm_rtc_regs.h"
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/* Address of RTC instances */
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/* RTC base address */
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#define HPM_RTC_BASE (0xF5044000UL)
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/* RTC base pointer */
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#define HPM_RTC ((RTC_Type *) HPM_RTC_BASE)
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#include "hpm_bkey_regs.h"
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/* Address of BKEY instances */
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/* BKEY base address */
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#define HPM_BKEY_BASE (0xF5048000UL)
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/* BKEY base pointer */
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#define HPM_BKEY ((BKEY_Type *) HPM_BKEY_BASE)
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#include "hpm_bmon_regs.h"
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/* Address of BMON instances */
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/* BMON base address */
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#define HPM_BMON_BASE (0xF504C000UL)
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/* BMON base pointer */
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#define HPM_BMON ((BMON_Type *) HPM_BMON_BASE)
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#include "hpm_tamp_regs.h"
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/* Address of TAMP instances */
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/* TAMP base address */
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#define HPM_TAMP_BASE (0xF5050000UL)
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/* TAMP base pointer */
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#define HPM_TAMP ((TAMP_Type *) HPM_TAMP_BASE)
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#include "hpm_mono_regs.h"
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/* Address of MONO instances */
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/* MONO base address */
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#define HPM_MONO_BASE (0xF5054000UL)
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/* MONO base pointer */
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#define HPM_MONO ((MONO_Type *) HPM_MONO_BASE)
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#include "riscv/riscv_core.h"
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#include "hpm_csr_regs.h"
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#include "hpm_interrupt.h"
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#include "hpm_misc.h"
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#include "hpm_dmamux_src.h"
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#include "hpm_trgmmux_src.h"
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#include "hpm_iomux.h"
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#include "hpm_pmic_iomux.h"
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#include "hpm_batt_iomux.h"
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#endif /* HPM_SOC_H */ |