159 lines
4.6 KiB
C
159 lines
4.6 KiB
C
/*
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* Copyright (c) 2021 hpmicro
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*
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*/
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#ifndef ETH_PHY_PORT_H
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#define ETH_PHY_PORT_H
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#include "hpm_ioc_regs.h"
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#include <rtdevice.h>
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#ifndef PHY_AUTO_NEGO
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#define PHY_AUTO_NEGO (1U)
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#endif
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#ifndef PHY_MDIO_CSR_CLK_FREQ
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#define PHY_MDIO_CSR_CLK_FREQ (200000000U)
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#endif
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enum phy_link_status
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{
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PHY_LINK_DOWN = 0U,
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PHY_LINK_UP
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};
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typedef struct {
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rt_uint32_t phy_speed;
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rt_uint32_t phy_duplex;
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} phy_info_t;
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typedef struct {
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rt_uint32_t phy_link;
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rt_phy_t phy;
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phy_info_t phy_info;
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} phy_device_t;
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#ifdef BSP_USING_ETH0
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#define RGMII (1U)
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/* DP83867 name and ID */
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#define PHY_NAME ("DP83867")
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#define PHY_ID1 (0x2000U)
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#define PHY_ID2 (0x28U)
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/* PHY_DP83867 basic control register */
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#define PHY_BASIC_CONTROL_REG (0x00U)
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#define PHY_RESET_MASK (1U << 15)
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#define PHY_AUTO_NEGOTIATION_MASK (1U << 12)
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/* PHY_DP83867 basic status register */
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#define PHY_BASIC_STATUS_REG (0x01U)
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#define PHY_LINKED_STATUS_MASK (1U << 2)
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#define PHY_AUTONEGO_COMPLETE_MASK (1U << 5)
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/* PHY_DP83867 ID one register */
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#define PHY_ID1_REG (0x02U)
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/* PHY_DP83867 ID two register */
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#define PHY_ID2_REG (0x03U)
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/* PHY_DP83867 auto-negotiate advertise register */
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#define PHY_AUTONEG_ADVERTISE_REG (0x04U)
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/* PHY_DP83867 status register */
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#define PHY_STATUS_REG (0x11U)
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#define PHY_100M_MASK (1UL << 14)
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#define PHY_1000M_MASK (1UL << 15)
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#define PHY_FULL_DUPLEX_MASK (1UL << 13)
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#define PHY_STATUS_SPEED_100M(SR) ((SR) & PHY_100M_MASK)
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#define PHY_STATUS_SPEED_1000M(SR) ((SR) & PHY_1000M_MASK)
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#define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK)
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#define PHY_SPEED_SEL_SHIFT (14U)
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/* PHY_DP83867 interrupt control register */
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#define PHY_INTERTUPT_CTRL_REG (0x12U)
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/* PHY_DP83867 interrupt status register */
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#define PHY_INTERRUPT_STATUS_REG (0x13U)
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/* PHY register index */
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typedef enum {
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PHY_BASIC_CONTROL_REG_IDX = 0,
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PHY_BASIC_STATUS_REG_IDX,
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PHY_ID1_REG_IDX,
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PHY_ID2_REG_IDX,
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PHY_AUTONEG_ADVERTISE_REG_IDX,
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PHY_STATUS_REG_IDX,
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PHY_INTERRUPT_FLAG_REG_IDX,
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PHY_INTERRUPT_MASK_REG_IDX
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} phy_reg_idx_t;
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/* ETH0 PHY register list */
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#define PHY0_REG_LIST PHY_BASIC_CONTROL_REG,\
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PHY_BASIC_STATUS_REG,\
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PHY_ID1_REG,\
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PHY_ID2_REG,\
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PHY_AUTONEG_ADVERTISE_REG,\
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PHY_STATUS_REG,\
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PHY_INTERTUPT_CTRL_REG,\
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PHY_INTERRUPT_STATUS_REG
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#else
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#define RMII (1U)
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/* DP83848 name and ID */
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#define PHY_NAME ("DP83848")
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#define PHY_ID1 (0x2000U)
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#define PHY_ID2 (0x17U)
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/* DP83848 basic control register */
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#define PHY_BASIC_CONTROL_REG (0x00U)
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#define PHY_RESET_MASK (1U << 15)
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#define PHY_AUTO_NEGOTIATION_MASK (1U << 12)
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/* DP83848 basic status register */
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#define PHY_BASIC_STATUS_REG (0x01U)
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#define PHY_LINKED_STATUS_MASK (1U << 2)
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#define PHY_AUTONEGO_COMPLETE_MASK (1U << 5)
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/* DP83848 ID one register */
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#define PHY_ID1_REG (0x02U)
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/* DP83848 ID two register */
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#define PHY_ID2_REG (0x03U)
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/* DP83848 auto-negotiate advertise register */
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#define PHY_AUTONEG_ADVERTISE_REG (0x04U)
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/* DP83848 status register */
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#define PHY_STATUS_REG (0x10U)
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#define PHY_10M_MASK (1UL << 1)
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#define PHY_FULL_DUPLEX_MASK (1UL << 2)
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#define PHY_STATUS_SPEED_10M(SR) ((SR) & PHY_10M_MASK)
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#define PHY_STATUS_FULL_DUPLEX(SR) ((SR) & PHY_FULL_DUPLEX_MASK)
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/* PHY register index */
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typedef enum {
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PHY_BASIC_CONTROL_REG_IDX = 0,
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PHY_BASIC_STATUS_REG_IDX,
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PHY_ID1_REG_IDX,
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PHY_ID2_REG_IDX,
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PHY_AUTONEG_ADVERTISE_REG_IDX,
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PHY_STATUS_REG_IDX,
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} phy_reg_idx_t;
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/* ETH0 PHY register list */
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#define PHY1_REG_LIST PHY_BASIC_CONTROL_REG,\
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PHY_BASIC_STATUS_REG,\
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PHY_ID1_REG,\
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PHY_ID2_REG,\
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PHY_AUTONEG_ADVERTISE_REG,\
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PHY_STATUS_REG
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#endif
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#endif
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