140 lines
4.5 KiB
C
140 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* sunxi RTC ccu driver
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*
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* Copyright (c) 2020, DaLv <lvda@allwinnertech.com>
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*/
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#include "ccu.h"
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#include "ccu_common.h"
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#include "ccu_reset.h"
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#include "ccu_div.h"
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#include "ccu_gate.h"
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#include "ccu_mp.h"
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#include "ccu_mult.h"
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#include "ccu_nk.h"
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#include "ccu_nkm.h"
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#include "ccu_nkmp.h"
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#include "ccu_nm.h"
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#include "ccu_phase.h"
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#include "ccu-sun8iw20-rtc.h"
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/*
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* iosc clk:
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*/
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static SUNXI_CCU_GATE(iosc_clk, "iosc", "rc-16m", 0x160, BIT(0), 0);
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static SUNXI_CCU_GATE_WITH_KEY(ext32k_gate_clk, "ext32k-gate",
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"ext-32k", 0x0,
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KEY_FIELD_MAGIC_NUM_RTC,
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BIT(4), 0);
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static CLK_FIXED_FACTOR(iosc_div32k_clk, "iosc-div32k", "iosc", 500, 1, 0);
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/*
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* osc32k clk(losc)
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*/
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static const char *const osc32k_parents[] = { "iosc-div32k", "ext32k-gate" };
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static SUNXI_CCU_MUX_WITH_GATE_KEY(osc32k_clk, "osc32k", osc32k_parents,
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0x0, 0, 1,
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KEY_FIELD_MAGIC_NUM_RTC, 0, 0);
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static SUNXI_CCU_GATE_WITH_FIXED_RATE(dcxo24M_div32k_clk, "dcxo24M-div32k",
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"dcxo24M", 0x60,
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32768, BIT(16));
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/*
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* rtc-1k clock
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*/
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static const char *const rtc32k_clk_parents[] = { "osc32k", "dcxo24M-div32k"};
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static SUNXI_CCU_MUX_WITH_GATE_KEY(rtc32k_clk, "rtc32k", rtc32k_clk_parents,
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0x0, 1, 1,
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KEY_FIELD_MAGIC_NUM_RTC, 0, 0);
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static CLK_FIXED_FACTOR(rtc_1k_clk, "rtc-1k", "rtc32k", 32, 1, 0);
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/* rtc-32k-fanout: only for debug */
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static const char *const rtc_32k_fanout_clk_parents[] = { "osc32k", "ext32k-gate",
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"dcxo24M-div32k"
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};
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static SUNXI_CCU_MUX_WITH_GATE(rtc_32k_fanout_clk, "rtc-32k-fanout",
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rtc_32k_fanout_clk_parents, 0x60, 1,
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2, BIT(0), 0);
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/* TODO: should add the div func */
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static SUNXI_CCU_GATE(rtc_spi_clk, "rtc-spi", "r-ahb", 0x310, BIT(31), 0);
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static struct ccu_common *sun8iw20_rtc_ccu_clks[] =
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{
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&iosc_clk.common,
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&ext32k_gate_clk.common,
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&osc32k_clk.common,
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&dcxo24M_div32k_clk.common,
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&rtc32k_clk.common,
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&rtc_32k_fanout_clk.common,
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&rtc_spi_clk.common,
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};
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static struct clk_hw_onecell_data sun8iw20_rtc_ccu_hw_clks =
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{
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.hws = {
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[CLK_IOSC] = &iosc_clk.common.hw,
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[CLK_EXT32K_GATE] = &ext32k_gate_clk.common.hw,
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[CLK_IOSC_DIV32K] = &iosc_div32k_clk.hw,
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[CLK_OSC32K] = &osc32k_clk.common.hw,
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[CLK_DCXO24M_DIV32K] = &dcxo24M_div32k_clk.common.hw,
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[CLK_RTC32K] = &rtc32k_clk.common.hw,
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[CLK_RTC_1K] = &rtc_1k_clk.hw,
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[CLK_RTC_32K_FANOUT] = &rtc_32k_fanout_clk.common.hw,
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[CLK_RTC_SPI] = &rtc_spi_clk.common.hw,
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},
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.num = CLK_RTC_NUMBER,
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};
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static const struct sunxi_ccu_desc sun8iw20_rtc_ccu_desc =
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{
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.ccu_clks = sun8iw20_rtc_ccu_clks,
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.num_ccu_clks = ARRAY_SIZE(sun8iw20_rtc_ccu_clks),
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.hw_clks = &sun8iw20_rtc_ccu_hw_clks,
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.clk_type = HAL_SUNXI_RTC_CCU,
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};
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static void clock_source_init(unsigned long base)
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{
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/* (1) enable DCXO */
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/* by default, DCXO_EN = 1. We don't have to do this... */
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set_reg(base + XO_CTRL_REG, 0x1, 1, 1);
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/* (2) enable auto switch function */
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/*
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* In some cases, we boot with auto switch function disabled, and try to
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* enable the auto switch function by rebooting.
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* But the rtc default value does not change unless vcc-rtc is loss.
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* So we should not rely on the default value of reg.
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* BIT(14): LOSC auto switch 32k clk source sel enable. 1: enable
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* BIT(15): LOSC auto switch function disable. 1: disable
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*/
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set_reg_key(base + LOSC_CTRL_REG,
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KEY_FIELD_MAGIC_NUM_RTC >> 16, 16, 16,
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0x1, 2, 14);
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/* (3) set the parent of osc32k-sys to ext-osc32k */
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set_reg_key(base + LOSC_CTRL_REG,
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KEY_FIELD_MAGIC_NUM_RTC >> 16, 16, 16,
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0x1, 1, 0);
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/* (4) set the parent of osc32k-out to osc32k-sys */
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/* by default, LOSC_OUT_SRC_SEL = 0x0. We don't have to do this... */
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set_reg(base + LOSC_OUT_GATING_REG,
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0x0, 2, 1);
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}
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int sunxi_rtc_ccu_init(void)
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{
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unsigned long reg = (unsigned long)SUNXI_RTC_CCU_REG;
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clock_source_init(reg);
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return ccu_common_init(reg, &sun8iw20_rtc_ccu_desc);
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}
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