130 lines
3.2 KiB
C
130 lines
3.2 KiB
C
/* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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*the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <hal_clk.h>
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void hal_clock_init(void)
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{
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CCMU_TRACE();
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clk_init();
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}
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hal_clk_t hal_clock_get(hal_clk_type_t type, hal_clk_id_t id)
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{
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CCMU_TRACE();
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return clk_get(type, id);
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}
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hal_clk_status_t hal_clock_put(hal_clk_t clk)
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{
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CCMU_TRACE();
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return clk_put(clk);
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}
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hal_clk_status_t hal_clk_set_parent(hal_clk_t clk, hal_clk_t parent)
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{
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CCMU_TRACE();
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return clk_set_parent(clk, parent);
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}
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hal_clk_t hal_clk_get_parent(hal_clk_t clk)
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{
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CCMU_TRACE();
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return clk_get_parent(clk);
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}
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u32 hal_clk_recalc_rate(hal_clk_t clk)
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{
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u32 rate = 0;
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CCMU_TRACE();
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clk_recalc_rate(clk, &rate);
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return rate;
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}
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u32 hal_clk_round_rate(hal_clk_t clk, u32 rate)
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{
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u32 round_rate = 0;
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CCMU_TRACE();
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clk_round_rate(clk, rate, &round_rate);
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return round_rate;
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}
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u32 hal_clk_get_rate(hal_clk_t clk)
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{
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u32 rate;
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CCMU_TRACE();
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clk_get_rate(clk, &rate);
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return rate;
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}
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hal_clk_status_t hal_clk_set_rate(hal_clk_t clk, u32 rate)
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{
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hal_clk_status_t ret;
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CCMU_TRACE();
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ret = clk_set_rate(clk, rate);
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return ret;
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}
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hal_clk_status_t hal_clock_is_enabled(hal_clk_t clk)
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{
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CCMU_TRACE();
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return clk_is_enabled(clk);
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}
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hal_clk_status_t hal_clock_enable(hal_clk_t clk)
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{
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hal_clk_status_t ret;
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CCMU_TRACE();
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ret = clk_prepare_enable(clk);
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return ret;
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}
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hal_clk_status_t hal_clock_disable(hal_clk_t clk)
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{
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hal_clk_status_t ret;
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CCMU_TRACE();
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ret = clk_disable_unprepare(clk);
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return ret;
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}
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