429 lines
21 KiB
C
429 lines
21 KiB
C
//*****************************************************************************
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//
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// hw_epi.h - Macros for use in accessing the EPI registers.
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//
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// Copyright (c) 2008-2009 Luminary Micro, Inc. All rights reserved.
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// Software License Agreement
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//
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// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
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// exclusively on LMI's microcontroller products.
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//
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// The software is owned by LMI and/or its suppliers, and is protected under
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// applicable copyright laws. All rights are reserved. You may not combine
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// this software with "viral" open-source software in order to form a larger
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// program. Any use in violation of the foregoing restrictions may subject
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// the user to criminal sanctions under applicable laws, as well as to civil
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// liability for the breach of the terms and conditions of this license.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 4694 of the Stellaris Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_EPI_H__
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#define __HW_EPI_H__
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//*****************************************************************************
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//
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// The following are defines for the External Peripheral Interface (EPI)
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//
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//*****************************************************************************
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#define EPI_O_CFG 0x00000000 // EPI Configuration
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#define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate
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#define EPI_O_GPCFG 0x00000010 // EPI General Purpose
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// Configuration
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#define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Mode Configuration
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#define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Mode
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// Configuration
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#define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2
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#define EPI_O_SDRAMCFG2 0x00000014 // EPI SDRAM Configuration 2
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#define EPI_O_GPCFG2 0x00000014 // EPI General-Purpose
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// Configuration 2
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#define EPI_O_ADDRMAP 0x0000001C // EPI Address Map
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#define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0
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#define EPI_O_RADDR0 0x00000024 // EPI Read Address 0
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#define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0
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#define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1
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#define EPI_O_RADDR1 0x00000034 // EPI Read Address 1
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#define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1
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#define EPI_O_STAT 0x00000060 // EPI Status
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#define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count
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#define EPI_O_READFIFO 0x00000070 // EPI Read FIFO
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#define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1
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#define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2
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#define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3
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#define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4
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#define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5
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#define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6
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#define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7
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#define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects
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#define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count
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#define EPI_O_IM 0x00000210 // EPI Interrupt Mask
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#define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status
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#define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status
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#define EPI_O_EISC 0x0000021C // EPI Error Interrupt Status and
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// Clear
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_CFG register.
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//
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//*****************************************************************************
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#define EPI_CFG_BLKEN 0x00000010 // Block Enable.
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#define EPI_CFG_MODE_M 0x0000000F // Mode Select.
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#define EPI_CFG_MODE_NONE 0x00000000 // None
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#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM
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#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8)
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_BAUD register.
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//
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//*****************************************************************************
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#define EPI_BAUD_COUNT_M 0x0000FFFF // Baud Rate Counter.
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#define EPI_BAUD_COUNT_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
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//
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//*****************************************************************************
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#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // Frequency Range.
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#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0
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#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15
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#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30
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#define EPI_SDRAMCFG_FREQ_50MHZ 0xC0000000 // 50
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#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter.
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#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode.
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#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM.
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#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64Mb (8MB)
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#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128Mb (16MB)
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#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256Mb (32MB)
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#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512Mb (64MB)
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#define EPI_SDRAMCFG_RFSH_S 16
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_GPCFG register.
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//
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//*****************************************************************************
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#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin.
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#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated.
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#define EPI_GPCFG_RDYEN 0x10000000 // Ready Enable.
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#define EPI_GPCFG_FRMPIN 0x08000000 // Framing Pin.
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#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame.
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#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count.
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#define EPI_GPCFG_RW 0x00200000 // Read and Write.
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#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes.
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#define EPI_GPCFG_RD2CYC 0x00040000 // 2-Cycle Reads.
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#define EPI_GPCFG_MAXWAIT_M 0x0000FF00 // Maximum Wait.
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#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size.
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#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address
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#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // 4 Bits Wide (EPI24 to EPI27)
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#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // 12 Bits Wide (EPI16 to EPI27).
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// Cannot be used with 24-bit data
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#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // 20 Bits Wide
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#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus.
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#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 4 Bits Wide (EPI0 to EPI7)
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#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0 to EPI15)
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#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0 to EPI23)
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#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide. May not be used
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// with clock (EPI0 to EPI31). This
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// value is normally used for
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// acquisition input and actuator
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// control as well as other general
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// purpose uses.
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#define EPI_GPCFG_FRMCNT_S 22
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#define EPI_GPCFG_MAXWAIT_S 8
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_HB8CFG register.
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//
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//*****************************************************************************
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#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable.
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#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable.
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#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity.
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#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity.
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#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait.
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#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States.
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#define EPI_HB8CFG_WRWS_0 0x00000000 // No wait states
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#define EPI_HB8CFG_WRWS_1 0x00000040 // 1 wait state
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#define EPI_HB8CFG_WRWS_2 0x00000080 // 2 wait states
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#define EPI_HB8CFG_WRWS_3 0x000000C0 // 3 wait states
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#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States.
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#define EPI_HB8CFG_RDWS_0 0x00000000 // No wait states
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#define EPI_HB8CFG_RDWS_1 0x00000010 // 1 wait state
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#define EPI_HB8CFG_RDWS_2 0x00000020 // 2 wait states
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#define EPI_HB8CFG_RDWS_3 0x00000030 // 3 wait states
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#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode.
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#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0]
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#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0]
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#define EPI_HB8CFG_MODE_SRAM 0x00000002 // SRAM
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#define EPI_HB8CFG_MODE_FIFO 0x00000003 // FIFO - D[7:0]
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#define EPI_HB8CFG_MAXWAIT_S 8
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_ADDRMAP register.
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//
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//*****************************************************************************
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#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size.
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#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 0x100 (256)
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#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 0x10000 (64 KB)
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#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 0x1000000 (16 MB)
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#define EPI_ADDRMAP_EPSZ_512MB 0x000000C0 // 0x20000000 (512 MB)
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#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address.
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#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped
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#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA0000000
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#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC0000000
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#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size.
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#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 0x100 (256)
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#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 0x10000 (64KB)
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#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 0x1000000 (16MB)
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#define EPI_ADDRMAP_ERSZ_512MB 0x0000000C // 0x20000000 (512MB)
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#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address.
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#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped
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#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x60000000
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#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x80000000
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_RSIZE0 register.
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//
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//*****************************************************************************
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#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size.
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#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits)
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#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits)
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#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits)
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_RADDR0 register.
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//
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//*****************************************************************************
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#define EPI_RADDR0_ADDR_M 0x1FFFFFFF // Current Address.
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#define EPI_RADDR0_ADDR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_RPSTD0 register.
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//
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//*****************************************************************************
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#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count.
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#define EPI_RPSTD0_POSTCNT_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_RSIZE1 register.
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//
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//*****************************************************************************
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#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size.
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#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits)
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#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits)
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#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits)
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_RADDR1 register.
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//
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//*****************************************************************************
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#define EPI_RADDR1_ADDR_M 0x1FFFFFFF // Current Address.
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#define EPI_RADDR1_ADDR_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_RPSTD1 register.
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//
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//*****************************************************************************
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#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count.
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#define EPI_RPSTD1_POSTCNT_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
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//
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//*****************************************************************************
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#define EPI_RFIFOCNT_COUNT_M 0x00000007 // FIFO Count.
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#define EPI_RFIFOCNT_COUNT_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_READFIFO register.
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//
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//*****************************************************************************
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#define EPI_READFIFO_DATA_M 0xFFFFFFFF // Reads Data.
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#define EPI_READFIFO_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_READFIFO1
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// register.
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//
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//*****************************************************************************
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#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data.
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#define EPI_READFIFO1_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_READFIFO2
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// register.
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//
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//*****************************************************************************
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#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data.
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#define EPI_READFIFO2_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_READFIFO3
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// register.
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//
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//*****************************************************************************
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#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data.
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#define EPI_READFIFO3_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_READFIFO4
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// register.
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//
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//*****************************************************************************
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#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data.
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#define EPI_READFIFO4_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_READFIFO5
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// register.
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//
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//*****************************************************************************
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#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data.
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#define EPI_READFIFO5_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_READFIFO6
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// register.
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//
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//*****************************************************************************
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#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data.
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#define EPI_READFIFO6_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_READFIFO7
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// register.
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//
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//*****************************************************************************
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#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data.
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#define EPI_READFIFO7_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_FIFOLVL register.
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//
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//*****************************************************************************
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#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error.
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#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error.
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#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO.
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#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Empty
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#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // >= 1/4 full
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#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // >= 1/2 full
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#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // >= 3/4 full
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#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO.
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#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty
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#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // <= 1/8 full
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#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // <= 1/4 full
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#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // <= 1/2 full
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#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // <= 3/4 full
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#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // <= 7/8 full
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#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries
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// in the NBRFIFO.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_IM register.
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//
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//*****************************************************************************
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#define EPI_IM_WRIM 0x00000004 // Write Interrupt Mask.
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#define EPI_IM_RDIM 0x00000002 // Read Interrupt Mask.
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#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_RIS register.
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//
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//*****************************************************************************
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#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status.
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#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status.
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#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_MIS register.
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//
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//*****************************************************************************
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#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status.
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#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status.
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#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_SDRAMCFG2
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// register.
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//
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//*****************************************************************************
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#define EPI_SDRAMCFG2_RCM 0x80000000 // Read Capture Mode.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
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//
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//*****************************************************************************
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#define EPI_HB8CFG2_WORD 0x80000000 // Word Access Mode.
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#define EPI_HB8CFG2_CSCFG 0x01000000 // Chip Select Configuration.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_GPCFG2 register.
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//
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//*****************************************************************************
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#define EPI_GPCFG2_WORD 0x80000000 // Word Access Mode.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_STAT register.
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//
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//*****************************************************************************
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#define EPI_STAT_CELOW 0x00000200 // Clock Enable Low.
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#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full.
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#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty.
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#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence.
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#define EPI_STAT_WBUSY 0x00000020 // Write Busy.
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#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy.
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#define EPI_STAT_ACTIVE 0x00000001 // Register Active.
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
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//
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//*****************************************************************************
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#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions.
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#define EPI_WFIFOCNT_WTAV_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the EPI_O_EISC register.
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//
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//*****************************************************************************
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#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error.
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#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error.
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#define EPI_EISC_TOUT 0x00000001 // Timeout Error.
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#endif // __HW_EPI_H__
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