65 lines
2.0 KiB
C
65 lines
2.0 KiB
C
/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-03-19 WangHuachen the first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <stdint.h>
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#include "drv_timer.h"
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#define TTC0_0_BASEADDR XPAR_PSU_TTC_0_BASEADDR
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#define TTC0_0_CLK_FREQ_HZ XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ
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static void rt_hw_timer_isr(int vector, void *param)
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{
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rt_tick_increase();
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/* clear interrupt */
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TTC_ISR(TTC0_0_BASEADDR);
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}
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static int rt_hw_timer_init(void)
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{
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/* Stop timer */
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TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_DIS_MASK;
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/* Initialize TTC */
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TTC_CNT_CNTRL(TTC0_0_BASEADDR) = TTC_CNT_CNTRL_RESET_VALUE;
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TTC_CLK_CNTRL(TTC0_0_BASEADDR) = 0x00;
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TTC_INTERVAL_VAL(TTC0_0_BASEADDR) = 0x00;
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TTC_MATCH_0(TTC0_0_BASEADDR) = 0x00;
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TTC_MATCH_1(TTC0_0_BASEADDR) = 0x00;
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TTC_MATCH_2(TTC0_0_BASEADDR) = 0x00;
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TTC_IER(TTC0_0_BASEADDR) = 0x00;
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TTC_ISR(TTC0_0_BASEADDR) = 0x00;
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/* Reset counter */
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TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_RST_MASK;
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/* Interval mode select */
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TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_INT_MASK;
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/* Setup interval */
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TTC_INTERVAL_VAL(TTC0_0_BASEADDR) = TTC0_0_CLK_FREQ_HZ / RT_TICK_PER_SECOND;
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/* Clear all of the prescaler control bits in the register */
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TTC_CLK_CNTRL(TTC0_0_BASEADDR) &= ~(TTC_CLK_CNTRL_PS_VAL_MASK |
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TTC_CLK_CNTRL_PS_EN_MASK);
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/* We do not need a prescaler*/
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/* Register the ticker handler with the GIC */
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rt_hw_interrupt_install(XPAR_XTTCPS_0_INTR, rt_hw_timer_isr, RT_NULL, "tick");
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/* Enable TTC interrupts in the GIC */
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rt_hw_interrupt_umask(XPAR_XTTCPS_0_INTR);
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/* Enable interval interrupt */
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TTC_IER(TTC0_0_BASEADDR) |= TTC_IXR_INTERVAL_MASK;
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/* Start timer */
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TTC_CNT_CNTRL(TTC0_0_BASEADDR) &=~ TTC_CNT_CNTRL_DIS_MASK;
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return RT_EOK;
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}
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INIT_BOARD_EXPORT(rt_hw_timer_init); |