454 lines
14 KiB
C
454 lines
14 KiB
C
/*
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* @brief LPC8xx clock driver
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*
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* @note
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* Copyright(C) NXP Semiconductors, 2012
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* All rights reserved.
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*
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* @par
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* LPC products. This software is supplied "AS IS" without any warranties of
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* any kind, and NXP Semiconductors and its licenser disclaim any and
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* all warranties, express or implied, including all implied warranties of
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* merchantability, fitness for a particular purpose and non-infringement of
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* intellectual property rights. NXP Semiconductors assumes no responsibility
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* or liability for the use of the software, conveys no license or rights under any
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* patent, copyright, mask work right, or any other intellectual property rights in
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* or to any products. NXP Semiconductors reserves the right to make changes
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* in the software without notification. NXP Semiconductors also makes no
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* representation or warranty that such application will be suitable for the
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* specified use without further testing or modification.
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*
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* @par
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* Permission to use, copy, modify, and distribute this software and its
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* documentation is hereby granted, under NXP Semiconductors' and its
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* licensor's relevant copyrights in the software, without fee, provided that it
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* is used in conjunction with NXP Semiconductors microcontrollers. This
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* copyright, permission, and disclaimer notice must appear in all copies of
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* this code.
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*/
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#ifndef __CLOCK_8XX_H_
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#define __CLOCK_8XX_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @defgroup CLOCK_8XX CHIP: LPC8xx Clock Driver
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* @ingroup CHIP_8XX_Drivers
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* @{
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*/
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/* Internal oscillator frequency */
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#define SYSCTL_IRC_FREQ (12000000)
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#ifndef MAX_CLOCK_FREQ
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#define MAX_CLOCK_FREQ (30000000)
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#endif
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/**
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* Clock sources for system and USB PLLs
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*/
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typedef enum CHIP_SYSCTL_PLLCLKSRC {
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SYSCTL_PLLCLKSRC_IRC = 0, /*!< Internal oscillator */
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SYSCTL_PLLCLKSRC_SYSOSC, /*!< Crystal (system) oscillator */
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SYSCTL_PLLCLKSRC_RESERVED,
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SYSCTL_PLLCLKSRC_EXT_CLKIN, /*!< External clock input */
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} CHIP_SYSCTL_PLLCLKSRC_T;
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/**
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* Watchdog oscillator analog output frequency selection
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* values enum (plus or minus 40%)
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*/
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typedef enum CHIP_WDTLFO_OSC {
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WDTLFO_OSC_ILLEGAL,
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WDTLFO_OSC_0_60, /*!< 0.6 MHz watchdog/LFO rate */
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WDTLFO_OSC_1_05, /*!< 1.05 MHz watchdog/LFO rate */
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WDTLFO_OSC_1_40, /*!< 1.4 MHz watchdog/LFO rate */
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WDTLFO_OSC_1_75, /*!< 1.75 MHz watchdog/LFO rate */
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WDTLFO_OSC_2_10, /*!< 2.1 MHz watchdog/LFO rate */
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WDTLFO_OSC_2_40, /*!< 2.4 MHz watchdog/LFO rate */
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WDTLFO_OSC_2_70, /*!< 2.7 MHz watchdog/LFO rate */
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WDTLFO_OSC_3_00, /*!< 3.0 MHz watchdog/LFO rate */
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WDTLFO_OSC_3_25, /*!< 3.25 MHz watchdog/LFO rate */
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WDTLFO_OSC_3_50, /*!< 3.5 MHz watchdog/LFO rate */
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WDTLFO_OSC_3_75, /*!< 3.75 MHz watchdog/LFO rate */
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WDTLFO_OSC_4_00, /*!< 4.0 MHz watchdog/LFO rate */
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WDTLFO_OSC_4_20, /*!< 4.2 MHz watchdog/LFO rate */
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WDTLFO_OSC_4_40, /*!< 4.4 MHz watchdog/LFO rate */
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WDTLFO_OSC_4_60 /*!< 4.6 MHz watchdog/LFO rate */
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} CHIP_WDTLFO_OSC_T;
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/**
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* Clock sources for main system clock
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*/
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typedef enum CHIP_SYSCTL_MAINCLKSRC {
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SYSCTL_MAINCLKSRC_IRC = 0, /*!< Internal oscillator */
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SYSCTL_MAINCLKSRC_PLLIN, /*!< System PLL input */
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SYSCTL_MAINCLKSRC_WDTOSC, /*!< Watchdog oscillator rate */
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SYSCTL_MAINCLKSRC_PLLOUT, /*!< System PLL output */
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} CHIP_SYSCTL_MAINCLKSRC_T;
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/**
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* System and peripheral clocks enum
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*/
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typedef enum CHIP_SYSCTL_CLOCK {
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SYSCTL_CLOCK_SYS = 0, /*!< System clock */
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SYSCTL_CLOCK_ROM, /*!< ROM clock */
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SYSCTL_CLOCK_RAM, /*!< RAM clock */
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SYSCTL_CLOCK_FLASHREG, /*!< FLASH register interface clock */
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SYSCTL_CLOCK_FLASH, /*!< FLASH array access clock */
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SYSCTL_CLOCK_I2C0, /*!< I2C0 clock */
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SYSCTL_CLOCK_GPIO, /*!< GPIO clock */
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SYSCTL_CLOCK_SWM, /*!< Switch matrix clock */
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SYSCTL_CLOCK_SCT, /*!< State configurable timer clock */
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SYSCTL_CLOCK_WKT, /*!< Self wake-up timer clock */
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SYSCTL_CLOCK_MRT, /*!< Multi-rate timer clock */
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SYSCTL_CLOCK_SPI0, /*!< SPI0 clock */
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SYSCTL_CLOCK_SPI1, /*!< SPI01 clock */
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SYSCTL_CLOCK_CRC, /*!< CRC clock */
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SYSCTL_CLOCK_UART0, /*!< UART0 clock */
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SYSCTL_CLOCK_UART1, /*!< UART1 clock */
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SYSCTL_CLOCK_UART2, /*!< UART2 clock */
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SYSCTL_CLOCK_WWDT, /*!< Watchdog clock */
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SYSCTL_CLOCK_IOCON, /*!< IOCON clock */
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SYSCTL_CLOCK_ACOMP, /*!< Analog comparator clock */
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/* LPC82x Specific Clocks */
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SYSCTL_CLOCK_I2C1 = 21, /*!< I2C1 Clock */
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SYSCTL_CLOCK_I2C2, /*!< I2C2 Clock */
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SYSCTL_CLOCK_I2C3, /*!< I2C3 Clock */
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SYSCTL_CLOCK_ADC, /*!< 12-Bit ADC Clock */
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SYSCTL_CLOCK_MTB = 26, /*!< Macro Trace Buffer [USED FOR DEBUGGING] */
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SYSCTL_CLOCK_DMA = 29, /*!< DMA Clock */
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} CHIP_SYSCTL_CLOCK_T;
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/* Clock name alias */
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#define SYSCTL_CLOCK_I2C SYSCTL_CLOCK_I2C0
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#define SYSCTL_CLOCK_ACMP SYSCTL_CLOCK_ACOMP
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/**
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* Clock sources for CLKOUT
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*/
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typedef enum CHIP_SYSCTL_CLKOUTSRC {
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SYSCTL_CLKOUTSRC_IRC = 0, /*!< Internal oscillator for CLKOUT */
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SYSCTL_CLKOUTSRC_SYSOSC, /*!< System oscillator for CLKOUT */
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SYSCTL_CLKOUTSRC_WDTOSC, /*!< Watchdog oscillator for CLKOUT */
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SYSCTL_CLKOUTSRC_MAINSYSCLK, /*!< Main system clock for CLKOUT */
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} CHIP_SYSCTL_CLKOUTSRC_T;
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/**
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* @brief Set System PLL divider values
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* @param msel : PLL feedback divider value
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* @param psel : PLL post divider value
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* @return Nothing
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* @note See the user manual for how to setup the PLL
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*/
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STATIC INLINE void Chip_Clock_SetupSystemPLL(uint8_t msel, uint8_t psel)
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{
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LPC_SYSCTL->SYSPLLCTRL = (msel & 0x1F) | ((psel & 0x3) << 5);
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}
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/**
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* @brief Read System PLL status
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* @return true if the PLL is locked, false if not locked
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*/
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STATIC INLINE bool Chip_Clock_IsSystemPLLLocked(void)
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{
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return (bool) ((LPC_SYSCTL->SYSPLLSTAT & 1) != 0);
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}
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/**
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* @brief Setup Watchdog oscillator rate and divider
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* @param wdtclk : Selected watchdog clock rate
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* @param div : Watchdog divider value, even value between 2 and 64
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* @return Nothing
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* @note Watchdog rate = selected rate divided by divider rate
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*/
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STATIC INLINE void Chip_Clock_SetWDTOSC(CHIP_WDTLFO_OSC_T wdtclk, uint8_t div)
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{
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LPC_SYSCTL->WDTOSCCTRL = (((uint32_t) wdtclk) << 5) | ((div >> 1) - 1);
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}
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/**
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* @brief Returns the main clock source
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* @return Main clock source
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*/
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STATIC INLINE CHIP_SYSCTL_MAINCLKSRC_T Chip_Clock_GetMainClockSource(void)
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{
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return (CHIP_SYSCTL_MAINCLKSRC_T) (LPC_SYSCTL->MAINCLKSEL & ~SYSCTL_MAINCLKSEL_RESERVED);
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}
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/**
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* @brief Set system clock divider
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* @param div : divider for system clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255. The system clock
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* rate is the main system clock divided by this value.
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*/
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STATIC INLINE void Chip_Clock_SetSysClockDiv(uint32_t div)
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{
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LPC_SYSCTL->SYSAHBCLKDIV = div;
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}
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/**
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* @brief Enable system or peripheral clock
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* @param clk : Clock to enable
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* @return Nothing
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*/
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STATIC INLINE void Chip_Clock_EnablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
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{
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LPC_SYSCTL->SYSAHBCLKCTRL = (1 << clk) | (LPC_SYSCTL->SYSAHBCLKCTRL & ~SYSCTL_SYSAHBCLKCTRL_RESERVED);
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}
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/**
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* @brief Disable system or peripheral clock
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* @param clk : Clock to disable
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* @return Nothing
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*/
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STATIC INLINE void Chip_Clock_DisablePeriphClock(CHIP_SYSCTL_CLOCK_T clk)
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{
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LPC_SYSCTL->SYSAHBCLKCTRL &= ~((1 << clk) | SYSCTL_SYSAHBCLKCTRL_RESERVED);
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}
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/**
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* @brief Set UART divider clock
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* @param div : divider for UART clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255. The UART clock
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* rate is the main system clock divided by this value.
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*/
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STATIC INLINE void Chip_Clock_SetUARTClockDiv(uint32_t div)
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{
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LPC_SYSCTL->UARTCLKDIV = div;
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}
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/**
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* @brief Return UART divider
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* @return divider for UART clock
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* @note A value of 0 means the clock is disabled.
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*/
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STATIC INLINE uint32_t Chip_Clock_GetUARTClockDiv(void)
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{
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return LPC_SYSCTL->UARTCLKDIV & ~SYSCTL_UARTCLKDIV_RESERVED;
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}
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/**
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* @brief Set The USART Fractional Generator Divider
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* @param div : Fractional Generator Divider value, should be 0xFF
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* @return Nothing
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*/
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STATIC INLINE void Chip_SYSCTL_SetUSARTFRGDivider(uint8_t div)
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{
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LPC_SYSCTL->UARTFRGDIV = (uint32_t) div;
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}
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/**
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* @brief Get The USART Fractional Generator Divider
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* @return Value of USART Fractional Generator Divider
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*/
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STATIC INLINE uint32_t Chip_SYSCTL_GetUSARTFRGDivider(void)
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{
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return LPC_SYSCTL->UARTFRGDIV & ~SYSCTL_UARTFRGDIV_RESERVED;
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}
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/**
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* @brief Set The USART Fractional Generator Multiplier
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* @param mult : An 8-bit value (0-255) U_PCLK = UARTCLKDIV/(1 + MULT/256)
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* @return Nothing
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*/
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STATIC INLINE void Chip_SYSCTL_SetUSARTFRGMultiplier(uint8_t mult)
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{
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LPC_SYSCTL->UARTFRGMULT = (uint32_t) mult;
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}
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/**
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* @brief Get The USART Fractional Generator Multiplier
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* @return Value of USART Fractional Generator Multiplier
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*/
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STATIC INLINE uint32_t Chip_SYSCTL_GetUSARTFRGMultiplier(void)
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{
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return LPC_SYSCTL->UARTFRGMULT & ~SYSCTL_UARTFRGMULT_RESERVED;
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}
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/**
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* @brief Set USART 0/1/2 UART base rate (up to main clock rate)
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* @param rate : Desired rate for fractional divider/multipler output
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* @param fEnable : true to use fractional clocking, false for integer clocking
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* @return Actual rate generated
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* @note USARTs 0 - 2 use the same base clock for their baud rate
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* basis. This function is used to generate that clock, while the
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* UART driver's SetBaud functions will attempt to get the closest
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* baud rate from this base clock without altering it. This needs
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* to be setup prior to individual UART setup.<br>
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* UARTs need a base clock 16x faster than the baud rate, so if you
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* need a 115.2Kbps baud rate, you will need a clock rate of at
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* least (115.2K * 16). The UART base clock is generated from the
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* main system clock, so fractional clocking may be the only
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* possible choice when using a low main system clock frequency.
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* Do not alter the FRGCLKDIV register after this call.
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*/
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uint32_t Chip_Clock_SetUSARTNBaseClockRate(uint32_t rate, bool fEnable);
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/**
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* @brief Get USART 0/1/2 UART base rate
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* @return USART 0/1/2 UART base rate
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*/
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uint32_t Chip_Clock_GetUSARTNBaseClockRate(void);
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/**
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* @brief Returns the main oscillator clock rate
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* @return main oscillator clock rate
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*/
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STATIC INLINE uint32_t Chip_Clock_GetMainOscRate(void)
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{
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return OscRateIn;
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}
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/**
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* @brief Returns the internal oscillator (IRC) clock rate
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* @return internal oscillator (IRC) clock rate
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*/
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STATIC INLINE uint32_t Chip_Clock_GetIntOscRate(void)
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{
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return SYSCTL_IRC_FREQ;
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}
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/**
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* @brief Returns the external clock input rate
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* @return External clock input rate
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*/
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STATIC INLINE uint32_t Chip_Clock_GetExtClockInRate(void)
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{
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return ExtRateIn;
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}
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/**
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* @brief Set System PLL clock source
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* @param src : Clock source for system PLL
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* @return Nothing
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* @note This function will also toggle the clock source update register
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* to update the clock source
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*/
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void Chip_Clock_SetSystemPLLSource(CHIP_SYSCTL_PLLCLKSRC_T src);
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/**
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* @brief Bypass System Oscillator and set oscillator frequency range
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* @param bypass : Flag to bypass oscillator
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* @param highfr : Flag to set oscillator range from 15-25 MHz
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* @return Nothing
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* @note Sets the PLL input to bypass the oscillator. This would be
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* used if an external clock that is not an oscillator is attached
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* to the XTALIN pin.
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*/
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void Chip_Clock_SetPLLBypass(bool bypass, bool highfr);
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/**
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* @brief Set main system clock source
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* @param src : Clock source for main system
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* @return Nothing
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* @note This function will also toggle the clock source update register
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* to update the clock source
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*/
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void Chip_Clock_SetMainClockSource(CHIP_SYSCTL_MAINCLKSRC_T src);
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/**
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* @brief Set CLKOUT clock source and divider
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* @param src : Clock source for CLKOUT
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* @param div : divider for CLKOUT clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255. The CLKOUT clock
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* rate is the clock source divided by the divider. This function will
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* also toggle the clock source update register to update the clock
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* source.
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*/
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void Chip_Clock_SetCLKOUTSource(CHIP_SYSCTL_CLKOUTSRC_T src, uint32_t div);
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/**
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* @brief Return estimated watchdog oscillator rate
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* @return Estimated watchdog oscillator rate
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* @note This rate is accurate to plus or minus 40%.
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*/
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uint32_t Chip_Clock_GetWDTOSCRate(void);
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/**
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* @brief Return System PLL input clock rate
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* @return System PLL input clock rate
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*/
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uint32_t Chip_Clock_GetSystemPLLInClockRate(void);
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/**
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* @brief Return System PLL output clock rate
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* @return System PLL output clock rate
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*/
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uint32_t Chip_Clock_GetSystemPLLOutClockRate(void);
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/**
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* @brief Return main clock rate
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* @return main clock rate
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*/
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uint32_t Chip_Clock_GetMainClockRate(void);
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/**
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* @brief Return system clock rate
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* @return system clock rate
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*/
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uint32_t Chip_Clock_GetSystemClockRate(void);
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/**
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* @brief Get IOCONCLKDIV clock rate
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* @param reg : Divider register to get
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* @return The clock rate going to the IOCON glitch filter
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* @note Use 0 to disable, or a divider value of 1 to 255.
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*/
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uint32_t Chip_Clock_GetIOCONCLKDIVClockRate(CHIP_PIN_CLKDIV_T reg);
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/**
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* @brief Set IOCONCLKDIV divider
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* @param reg : divider register to set
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* @param div : divider value for IOCONCLKDIV[reg] clock
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* @return Nothing
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* @note Use 0 to disable, or a divider value of 1 to 255.
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*/
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void Chip_Clock_SetIOCONCLKDIV(CHIP_PIN_CLKDIV_T reg, uint8_t div);
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/**
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* @}
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*/
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/** @defgroup IRC_8XX CHIP: LPC8xx IRC Configuration
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* @ingroup CHIP_8XX_Drivers
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* @{
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*/
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/**
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* @brief set main / system clock using IRC and PLL
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* @param main: main clock frequency (in MHz)
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* @param sys : system clock frequency (in MHz)
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* @return bool: Success = true / fail = false
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* @note This is a table based function. The table uses both the
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* main frequency and the system frequency to set the PLL.
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* All useful main / system clock combinations are in the table.
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* See irc_8xx.c for details.
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*/
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bool Chip_IRC_SetFreq(uint32_t main, uint32_t sys);
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/**
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* @brief Set main / system clock using IRC and PLL
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* @param sys : system clock frequency (in MHz)
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* @return Nothing
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* @note This function uses the ROM set_pll() function.
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*/
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void Chip_IRC_SetFreq_ROM(uint32_t sys);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CLOCK_8XX_H_ */
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