b9e4fcfc68
整合libcpu/riscv中的移植文件 提供一份公共代码于common 在提交本pr时,除hpmicro的内核,rv32内核bsp已完成去除大部分的冗余,大部分代码采用common中的实现。本pr的作用是进一步统一common中的文件,从而提供一份公用代码,新移植的RV32内核的BSP可以全部使用common代码。 - 在common中提供一份公用文件:interrupt_gcc.S - 修改原有的文件,将原有的中断中上下文切换代码替换为interrupt_gcc.S - 基于上述修改,修改仓库中risc-v内核的BSP与移植相关的部分 (主要包含中断入口函数 中断栈等) - 在common中提供一份公用文件:trap_common.c;提供统一中断入口函数,中断入口函数初始化,中断入口注册等函数,并完善异常时的信息输出 - 在common中提供一份公用文件:rt_hw_stack_frame.h;将栈帧结构体剥离,供用户使用 - 在上述工作完成后,在上述工作的基础上测试仓库中risc-v内核的BSP - 完善函数中的命名,完善中断栈的获取 - 提供一份详细的基于现有common文件的移植指南 #### 在什么测试环境下测试通过 - 1.CH32V307V-R1-R0 - 2.CH32V208W-R0-1V4 - 3.HPM6750EVKMINI - 4.GD32VF103V-EVAL - 5.qemu(CORE-V-MCU ) > 与上述开发板使用同样芯片的BSP均测试通过 在CH32V307V-R1-R0与HPM6750EVKMINI上基于现有移植文件进行多线程复杂场景下的长时间测试,测试过程系统运行正常。
113 lines
2.7 KiB
C
113 lines
2.7 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/28 Bernard The unify RISC-V porting code.
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* 2020/11/20 BalanceTWK Add FPU support
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* 2023/01/04 WangShun Adapt to CH32
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "cpuport.h"
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#include "rt_hw_stack_frame.h"
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#ifndef RT_USING_SMP
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volatile rt_ubase_t rt_interrupt_from_thread = 0;
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volatile rt_ubase_t rt_interrupt_to_thread = 0;
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volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
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#endif
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/**
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* This function will initialize thread stack
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*
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* @param tentry the entry of thread
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* @param parameter the parameter of entry
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* @param stack_addr the beginning stack address
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* @param texit the function will be called when thread exit
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*
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* @return stack address
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*/
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rt_uint8_t *rt_hw_stack_init(void *tentry,
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void *parameter,
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rt_uint8_t *stack_addr,
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void *texit)
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{
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struct rt_hw_stack_frame *frame;
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rt_uint8_t *stk;
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int i;
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stk = stack_addr + sizeof(rt_ubase_t);
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stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
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stk -= sizeof(struct rt_hw_stack_frame);
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frame = (struct rt_hw_stack_frame *)stk;
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for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
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{
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((rt_ubase_t *)frame)[i] = 0xdeadbeef;
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}
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frame->ra = (rt_ubase_t)texit;
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frame->a0 = (rt_ubase_t)parameter;
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frame->epc = (rt_ubase_t)tentry;
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/* force to machine mode(MPP=11) and set MPIE to 1 */
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#ifdef ARCH_RISCV_FPU
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frame->mstatus = 0x7880;
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#else
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frame->mstatus = 0x1880;
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#endif
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return stk;
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}
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rt_weak void rt_trigger_software_interrupt(void)
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{
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while (0);
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}
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rt_weak void rt_hw_do_after_save_above(void)
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{
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while (1);
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}
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/*
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
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* #else
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* void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
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* #endif
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*/
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#ifndef RT_USING_SMP
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rt_weak void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread)
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{
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if (rt_thread_switch_interrupt_flag == 0)
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rt_interrupt_from_thread = from;
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rt_interrupt_to_thread = to;
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rt_thread_switch_interrupt_flag = 1;
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rt_trigger_software_interrupt();
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return ;
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}
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#endif /* end of RT_USING_SMP */
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/** shutdown CPU */
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rt_weak void rt_hw_cpu_shutdown()
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{
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rt_base_t level;
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rt_kprintf("shutdown...\n");
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level = rt_hw_interrupt_disable();
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while (level)
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{
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RT_ASSERT(0);
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}
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}
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