50cb4be8ce
* bsp beaglebone: add IAR template files and fix it's build error ATTENTION: project.* was generated by scons, so I add it to gitignore. rtconfig.py *FLAGS located in "PLATFORM == 'iccarm'" are unverified and maybe wrong. （我只是从STM32里面抄来，然后根据自己的理解改了一下，并没有验证这些参数的正确性， 我也不知道怎么用命令行调用这些参数来编译） * bsp beaglebone: add beaglebone_ram.icf ROM address from uboot_cmd.txt am335x_DDR.icf use 0x82000000, different to uboot_cmd.txt & gcc beaglebone_ram.lds, the difference will easy cause later developer got below error: => go 0x80200000 ## Starting application at 0x80200000 ... undefined instruction pc : [<8200956c>] lr : [<8ff62497>] reloc pc : [<728a956c>] lr : [<80802497>] sp : 8df37358 ip : 00000000 fp : 00000002 r10: 8df4d448 r9 : 8df3feb8 r8 : 8ffd30f8 r7 : 8ff78089 r6 : 00000002 r5 : 80200000 r4 : 8df4d44c r3 : 80200000 r2 : 8df4d44c r1 : 8df4d44c r0 : 00000001 Flags: nzCv IRQs off FIQs on Mode SVC_32 Code: 5dbffcdd bb9bdf7f abf85423 eff1f77f (7ed7daaf) Resetting CPU ... resetting ... * libcpu am335x: context_iar.S rt_hw_context_switch: add thumb mode support IAR new project defualt Processor mode is Thumb, this will cause user easy occur the following error: ... msh />Execption: r00:0x8800aaa8 r01:0x802080c5 r02:0x00000000 r03:0x88009b4c r04:0x00001000 r05:0x00000000 r06:0x00001403 r07:0x00100000 r08:0x00000000 r09:0x00000000 r10:0x0000000a fp :0x0000000a ip :0x65687374 sp :0x00006c6c lr :0x0000008a pc :0x88008be0 cpsr:0x880001bc software interrupt shutdown... (0) assertion failed at function:rt_hw_cpu_shutdown, line number:160 * bsp beaglebone: change IAR template.ewp code use Arm mode Arm mode bin size will bigger than Thumb mode * libcpu am335x: IAR: use rt_hw_cpu_dcache_enable instead of rt_cpu_dcache_enable Reviewer mysterywolf say: 麻烦把rt_cpu_icache_enable 和 rt_cpu_dcache_enable, 统一改成 rt_hw_cpu_icache_enable 和 rt_hw_cpu_dcache_enable rt_hw_cpu_icache_enable 和 rt_hw_cpu_dcache_enable 是其他bsp也是这么命名的 这是个命名统一的函数
87 lines
2.5 KiB
ArmAsm
87 lines
2.5 KiB
ArmAsm
;/*
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; * Copyright (c) 2006-2021, RT-Thread Development Team
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; *
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; * SPDX-License-Identifier: Apache-2.0
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2011-08-14 weety copy from mini2440
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; * 2015-04-15 ArdaFu convert from context_gcc.s
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; */
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#define NOINT 0xc0
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SECTION .text:CODE(6)
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/*
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* rt_base_t rt_hw_interrupt_disable();
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*/
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PUBLIC rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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MRS R0, CPSR
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ORR R1, R0, #NOINT
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MSR CPSR_C, R1
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MOV PC, LR
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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PUBLIC rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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MSR CPSR_CXSF, R0
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MOV PC, LR
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/*
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* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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* r0 --> from
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* r1 --> to
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*/
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PUBLIC rt_hw_context_switch
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rt_hw_context_switch:
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STMFD SP!, {LR} ; push pc (lr should be pushed in place of PC)
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STMFD SP!, {R0-R12, LR} ; push lr & register file
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MRS R4, CPSR
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TST LR, #0x01
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ORRNE R4, R4, #0x20 ; it's thumb code
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STMFD SP!, {R4} ; push cpsr
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STR SP, [R0] ; store sp in preempted tasks TCB
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LDR SP, [R1] ; get new task stack pointer
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LDMFD SP!, {R4} ; pop new task spsr
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MSR SPSR_cxsf, R4
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LDMFD SP!, {R0-R12, LR, PC}^ ; pop new task r0-r12, lr & pc
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/*
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* void rt_hw_context_switch_to(rt_uint32 to);
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* r0 --> to
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*/
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PUBLIC rt_hw_context_switch_to
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rt_hw_context_switch_to:
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LDR SP, [R0] ; get new task stack pointer
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LDMFD SP!, {R4} ; pop new task spsr
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MSR SPSR_cxsf, R4
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BIC R4, R4, #0x20 ; must be ARM mode
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MSR CPSR_CXSF, R4
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LDMFD SP!, {R0-R12, LR, PC}^ ; pop new task r0-r12, lr & pc
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/*
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* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
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*/
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IMPORT rt_thread_switch_interrupt_flag
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IMPORT rt_interrupt_from_thread
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IMPORT rt_interrupt_to_thread
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PUBLIC rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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LDR R2, =rt_thread_switch_interrupt_flag
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LDR R3, [R2]
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CMP R3, #1
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BEQ _reswitch
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MOV R3, #1 ; set flag to 1
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STR R3, [R2]
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LDR R2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread
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STR R0, [R2]
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_reswitch:
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LDR R2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread
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STR R1, [R2]
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MOV PC, LR
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END
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