162 lines
3.4 KiB
C
162 lines
3.4 KiB
C
/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Email: opensource_embedded@phytium.com.cn
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*
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* Change Logs:
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* Date Author Notes
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* 2022-10-26 huanghe first commit
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* 2022-10-26 zhugengyu support aarch64
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* 2023-07-26 huanghe update psci uage
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*
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*/
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#include <rtthread.h>
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#include "board.h"
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#include <gicv3.h>
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#include "rtconfig.h"
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#include "phytium_cpu.h"
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#if defined(TARGET_ARMV8_AARCH64)
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#include "cpuport.h"
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#include "gtimer.h"
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#include "mmu.h"
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#include "cp15.h"
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#endif
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#ifdef RT_USING_SMP
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#include <interrupt.h>
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#if defined(TARGET_ARMV8_AARCH64)
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#include "psci.h"
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extern void _secondary_cpu_entry(void);
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#else
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extern void rt_secondary_cpu_entry(void);
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#endif
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#include "fpsci.h"
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rt_uint64_t rt_cpu_mpidr_early[] =
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{
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#if defined(TARGET_E2000D)
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[0] = 0x80000200,
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[1] = 0x80000201,
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#elif defined(TARGET_E2000Q) || defined(TARGET_PHYTIUMPI)
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[0] = 0x80000000,
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[1] = 0x80000100,
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[2] = 0x80000200,
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[3] = 0x80000201,
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#elif defined(TARGET_F2000_4) || defined(TARGET_D2000)
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[0] = 0x80000000,
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[1] = 0x80000001,
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[2] = 0x80000100,
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[3] = 0x80000101,
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#if defined(TARGET_D2000)
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[4] = 0x80000200,
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[5] = 0x80000201,
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[6] = 0x80000300,
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[7] = 0x80000301,
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#endif
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#endif
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};
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extern int rt_hw_timer_init(void);
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void rt_hw_secondary_cpu_up(void)
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{
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rt_uint32_t i;
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rt_uint32_t cpu_mask = 0;
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int cpu_id;
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cpu_id = rt_hw_cpu_id();
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rt_kprintf("rt_hw_secondary_cpu_up is processing \r\n");
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for (i = 0; i < RT_CPUS_NR; i++)
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{
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if (i == cpu_id)
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{
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continue;
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}
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cpu_mask = 1 << phytium_cpu_id_mapping(i);
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#if defined(TARGET_ARMV8_AARCH64)
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/* code */
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rt_kprintf("cpu_mask = 0x%x \n", cpu_mask);
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char *entry = (char *)_secondary_cpu_entry;
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entry += PV_OFFSET;
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FPsciCpuMaskOn(cpu_mask, (uintptr)entry);
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__DSB();
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#else
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/* code */
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char *entry = (char *)rt_secondary_cpu_entry;
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entry += PV_OFFSET;
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FPsciCpuMaskOn(cpu_mask, (uintptr)entry);
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__asm__ volatile("dsb" ::: "memory");
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#endif
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}
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}
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/**
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* This function will initialize board
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*/
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extern size_t MMUTable[];
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void rt_hw_secondary_cpu_bsp_start(void)
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{
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/* spin lock init */
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rt_hw_spin_lock(&_cpus_lock);
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/* mmu init */
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#if defined(TARGET_ARMV8_AARCH64)
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extern unsigned long MMUTable[];
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rt_hw_mmu_ktbl_set((unsigned long)MMUTable);
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#else
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rt_uint32_t mmutable_p;
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mmutable_p = (rt_uint32_t)MMUTable + (rt_uint32_t)PV_OFFSET ;
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rt_hw_mmu_switch(mmutable_p) ;
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#endif
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/* vector init */
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rt_hw_vector_init();
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/* interrupt init */
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#if defined(TARGET_ARMV8_AARCH64)
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arm_gic_cpu_init(0, 0);
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arm_gic_redist_init(0, 0);
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rt_kprintf("arm_gic_redist_init is over rt_hw_cpu_id() is %d \r\n", rt_hw_cpu_id());
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#else
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arm_gic_cpu_init(0);
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arm_gic_redist_init(0);
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#endif
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/* gtimer init */
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#if defined(TARGET_ARMV8_AARCH64)
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rt_hw_gtimer_init();
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#else
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rt_hw_timer_init();
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#endif
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rt_hw_interrupt_umask(RT_SCHEDULE_IPI);
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/* start scheduler */
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rt_kprintf("\rcall cpu %d on success\n", rt_hw_cpu_id());
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rt_hw_secondary_cpu_idle_exec();
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rt_system_scheduler_start();
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}
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void rt_hw_secondary_cpu_idle_exec(void)
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{
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#if defined(TARGET_ARMV8_AARCH64)
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__WFE();
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#else
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asm volatile("wfe" ::
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: "memory", "cc");
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#endif
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}
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#endif
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