371 lines
10 KiB
C
371 lines
10 KiB
C
/*
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* Copyright (c) 2019-2020
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#include <rthw.h>
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#include <rtdevice.h>
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#include <lwp_user_mm.h>
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#include <ioremap.h>
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#include "board.h"
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#include "drv_uart.h"
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#include "riscv_io.h"
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#include "board.h"
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#define UART_DEFAULT_BAUDRATE 115200
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#define UART_CLK 50000000
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#define UART_ADDR 0x91403000UL
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#define UART_IRQ 0x13
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#define UART_RBR (0x00) /* receive buffer register */
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#define UART_THR (0x00) /* transmit holding register */
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#define UART_DLL (0x00) /* divisor latch low register */
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#define UART_DLH (0x04) /* diviso latch high register */
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#define UART_IER (0x04) /* interrupt enable register */
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#define UART_IIR (0x08) /* interrupt identity register */
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#define UART_FCR (0x08) /* FIFO control register */
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#define UART_LCR (0x0c) /* line control register */
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#define UART_MCR (0x10) /* modem control register */
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#define UART_LSR (0x14) /* line status register */
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#define UART_MSR (0x18) /* modem status register */
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#define UART_SCH (0x1c) /* scratch register */
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#define UART_USR (0x7c) /* status register */
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#define UART_TFL (0x80) /* transmit FIFO level */
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#define UART_RFL (0x84) /* RFL */
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#define UART_HALT (0xa4) /* halt tx register */
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#define UART_DLF (0xc0) /* Divisor Latch Fraction Register */
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#define BIT(x) (1 << x)
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/* Line Status Rigster */
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#define UART_LSR_RXFIFOE (BIT(7))
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#define UART_LSR_TEMT (BIT(6))
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#define UART_LSR_THRE (BIT(5))
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#define UART_LSR_BI (BIT(4))
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#define UART_LSR_FE (BIT(3))
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#define UART_LSR_PE (BIT(2))
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#define UART_LSR_OE (BIT(1))
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#define UART_LSR_DR (BIT(0))
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#define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */
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/* Line Control Register */
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#define UART_LCR_DLAB (BIT(7))
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#define UART_LCR_SBC (BIT(6))
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#define UART_LCR_PARITY_MASK (BIT(5)|BIT(4))
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#define UART_LCR_EPAR (1 << 4)
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#define UART_LCR_OPAR (0 << 4)
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#define UART_LCR_PARITY (BIT(3))
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#define UART_LCR_STOP (BIT(2))
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#define UART_LCR_DLEN_MASK (BIT(1)|BIT(0))
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#define UART_LCR_WLEN5 (0)
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#define UART_LCR_WLEN6 (1)
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#define UART_LCR_WLEN7 (2)
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#define UART_LCR_WLEN8 (3)
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/* Halt Register */
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#define UART_HALT_LCRUP (BIT(2))
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#define UART_HALT_FORCECFG (BIT(1))
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#define UART_HALT_HTX (BIT(0))
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/* Interrupt Enable Register */
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#define UART_IER_MASK (0xff)
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#define UART_IER_PTIME (BIT(7))
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#define UART_IER_RS485 (BIT(4))
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#define UART_IER_MSI (BIT(3))
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#define UART_IER_RLSI (BIT(2))
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#define UART_IER_THRI (BIT(1))
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#define UART_IER_RDI (BIT(0))
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/* Interrupt ID Register */
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#define UART_IIR_FEFLAG_MASK (BIT(6)|BIT(7))
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#define UART_IIR_IID_MASK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
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#define UART_IIR_IID_MSTA (0)
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#define UART_IIR_IID_NOIRQ (1)
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#define UART_IIR_IID_THREMP (2)
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#define UART_IIR_IID_RXDVAL (4)
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#define UART_IIR_IID_LINESTA (6)
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#define UART_IIR_IID_BUSBSY (7)
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#define UART_IIR_IID_CHARTO (12)
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struct device_uart
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{
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rt_ubase_t hw_base;
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rt_uint32_t irqno;
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};
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static rt_err_t rt_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
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static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg);
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static int drv_uart_putc(struct rt_serial_device *serial, char c);
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static int drv_uart_getc(struct rt_serial_device *serial);
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const struct rt_uart_ops _uart_ops =
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{
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rt_uart_configure,
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uart_control,
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drv_uart_putc,
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drv_uart_getc,
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//TODO: add DMA support
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RT_NULL
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};
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struct rt_serial_device serial1;
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struct device_uart uart1;
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#define write32(addr, val) writel(val, (void*)(addr))
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#define read32(addr) readl((void*)(addr))
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static void _uart_init(void *uart_base)
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{
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uint32_t bdiv;
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uint32_t dlf;
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uint32_t dlh;
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uint32_t dll;
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bdiv = UART_CLK / UART_DEFAULT_BAUDRATE;
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dlh = bdiv >> 12;
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dll = (bdiv - (dlh << 12)) / 16;
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dlf = bdiv - (dlh << 12) - dll * 16;
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if(dlh == 0 && dll == 0)
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{
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dll = 1;
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dlf = 0;
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}
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write32(uart_base + UART_LCR, 0x00);
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/* Disable all interrupts */
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write32(uart_base + UART_IER, 0x00);
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/* Enable DLAB */
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write32(uart_base + UART_LCR, 0x80);
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if (bdiv) {
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/* Set divisor low byte */
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write32(uart_base + UART_DLL, dll);
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/* Set divisor high byte */
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write32(uart_base + UART_DLH, dlh);
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/* Set divisor fraction byte*/
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write32(uart_base + UART_DLF, dlf);
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}
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/* 8 bits, no parity, one stop bit */
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write32(uart_base + UART_LCR, 0x03);
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/* Enable FIFO */
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write32(uart_base + UART_FCR, 0x01);
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/* No modem control DTR RTS */
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write32(uart_base + UART_MCR, 0x00);
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/* Clear line status */
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read32(uart_base + UART_LSR);
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/* Read receive buffer */
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read32(uart_base + UART_RBR);
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read32(uart_base + UART_USR);
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read32(uart_base + UART_FCR);
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/* Set scratchpad */
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write32(uart_base + UART_SCH, 0x00);
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//enable uart rx irq
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// write32(uart_base + UART_IER, 0x01);
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}
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static void uart_set_isr(void *uart_base, uint8_t enable, uint32_t irq_type)
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{
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uint32_t value;
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value = read32(uart_base + UART_IER);
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if (enable)
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{
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value |= irq_type;
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}
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else
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{
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value &= ~irq_type;
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}
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write32(uart_base + UART_IER, value);
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}
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/*
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* UART interface
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*/
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static rt_err_t rt_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
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{
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return (RT_EOK);
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}
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static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg)
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{
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struct device_uart *uart = (struct device_uart*)serial->parent.user_data;
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#ifdef RT_USING_SERIAL_V2
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rt_ubase_t ctrl_flag = 0;
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rt_ubase_t ctrl_arg;
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#endif
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#ifdef RT_USING_SERIAL_V2
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ctrl_arg = (rt_ubase_t)arg;
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if (ctrl_arg & (RT_DEVICE_FLAG_RX_BLOCKING | RT_DEVICE_FLAG_RX_NON_BLOCKING))
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{
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ctrl_flag |= RT_DEVICE_FLAG_INT_RX;
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}
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#endif
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switch (cmd)
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{
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case RT_DEVICE_CTRL_CLR_INT:
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#ifdef RT_USING_SERIAL_V2
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if (ctrl_flag & RT_DEVICE_FLAG_INT_RX)
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#else
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if ((size_t)arg == RT_DEVICE_FLAG_INT_RX)
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#endif
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{
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uart_set_isr((void*)(uart->hw_base), 0, UART_IER_RDI);
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}
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break;
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case RT_DEVICE_CTRL_SET_INT:
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#ifdef RT_USING_SERIAL_V2
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if (ctrl_flag & RT_DEVICE_FLAG_INT_RX)
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#else
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if ((size_t)arg == RT_DEVICE_FLAG_INT_RX)
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#endif
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{
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uart_set_isr((void*)(uart->hw_base), 1, UART_IER_RDI);
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}
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break;
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#ifdef RT_USING_SERIAL_V2
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case RT_DEVICE_CTRL_CONFIG:
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if (ctrl_flag & RT_DEVICE_FLAG_INT_RX)
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{
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uart_set_isr((void*)(uart->hw_base), 1, UART_IER_RDI);
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}
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break;
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#endif
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case RT_FIOMMAP2:
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{
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struct dfs_mmap2_args *mmap2 = (struct dfs_mmap2_args *)arg;
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if (mmap2)
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{
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if (mmap2->length > 0x400)
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{
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return -RT_ENOMEM;
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}
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mmap2->ret = lwp_map_user_phy(lwp_self(), RT_NULL, (void*)(uart->hw_base), mmap2->length, 0);
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}
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break;
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}
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}
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return (RT_EOK);
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}
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static int drv_uart_putc(struct rt_serial_device *serial, char c)
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{
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volatile uint32_t *sed_buf;
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volatile uint32_t *sta;
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struct device_uart *uart = (struct device_uart*)serial->parent.user_data;
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sed_buf = (uint32_t *)(uart->hw_base + UART_THR);
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sta = (uint32_t *)(uart->hw_base + UART_USR);
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/* FIFO status, contain valid data */
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// while (!(*sta & 0x02));
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while (!(read32(uart->hw_base + UART_LSR) & 0x20));
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*sed_buf = c;
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return (1);
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}
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static int drv_uart_getc(struct rt_serial_device *serial)
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{
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struct device_uart *uart = (struct device_uart*)serial->parent.user_data;
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volatile uint32_t *lsr = (uint32_t *)(uart->hw_base + UART_LSR);
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volatile uint32_t *rbr = (uint32_t *)(uart->hw_base + UART_RBR);
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if (!(*lsr & UART_LSR_DR))
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{
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return -1;
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}
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return (int)*rbr;
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}
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static void rt_hw_uart_isr(int irq, void *param)
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{
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struct rt_serial_device *serial = (struct rt_serial_device*)param;
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struct device_uart *uart;
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size_t uart_base;
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uint32_t iir, lsr;
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uart = (struct device_uart*)serial->parent.user_data;
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uart_base = uart->hw_base;
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iir = readb((void*)(uart_base + UART_IIR)) & UART_IIR_IID_MASK;
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lsr = readb((void*)(uart_base + UART_LSR));
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// rt_kprintf("uart isr iir:%x lsr:%x\r\n", iir, lsr);
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if (iir == UART_IIR_IID_BUSBSY)
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{
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(void)readb((void*)(uart_base + UART_USR));
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}
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else if (lsr & (UART_LSR_DR | UART_LSR_BI))
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{
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#ifdef RT_USING_SERIAL_V2
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struct rt_serial_rx_fifo *rx_fifo;
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uint8_t data;
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rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
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RT_ASSERT(rx_fifo != RT_NULL);
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do {
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data = readb((void*)(uart_base + UART_RBR));
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rt_ringbuffer_putchar(&(rx_fifo->rb), data);
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lsr = readb((void*)(uart_base + UART_LSR));
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} while(lsr & UART_LSR_DR);
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#endif
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rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
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}
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else if (iir & UART_IIR_IID_CHARTO)
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/* has charto irq but no dr lsr? just read and ignore */
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{
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readb((void*)(uart_base + UART_RBR));
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}
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}
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/*
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* UART Initiation
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*/
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int rt_hw_uart_init(void)
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{
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struct rt_serial_device *serial;
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struct device_uart *uart;
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struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
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{
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serial = &serial1;
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uart = &uart1;
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serial->ops = &_uart_ops;
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serial->config = config;
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serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
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uart->hw_base = (rt_base_t)rt_ioremap((void *)UART_ADDR, 0x1000);
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uart->irqno = UART_IRQ;
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_uart_init((void*)(uart->hw_base));
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rt_hw_interrupt_install(uart->irqno, rt_hw_uart_isr, serial, "uart1");
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rt_hw_interrupt_umask(uart->irqno);
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rt_hw_serial_register(serial,
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RT_CONSOLE_DEVICE_NAME,
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RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
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uart);
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}
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return 0;
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}
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