66 lines
1.7 KiB
ArmAsm
66 lines
1.7 KiB
ArmAsm
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018/10/01 Bernard The first version
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* 2018/12/27 Jesven Add SMP support
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* 2020/6/12 Xim Port to QEMU and remove SMP support
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*/
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#define XSTATUS_FS (3 << 13) /* initial state of FPU, clear to disable */
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#define XSTATUS_PUM (1 << 18)
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#include <cpuport.h>
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boot_hartid: .int
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.global boot_hartid
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.global _start
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.section ".start", "ax"
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_start:
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#ifdef RISCV_S_MODE
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# save hartid
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la t0, boot_hartid # global varible rt_boot_hartid
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mv t1, a0 # get hartid in S-mode frome a0 register
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sw t1, (t0) # store t1 register low 4 bits in memory address which is stored in t0
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#else
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# setup stacks per hart
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csrr t0, mhartid # read current hart id
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slli t0, t0, 10 # shift left the hart id by 1024
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# park harts with id != 0
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csrr a0, mhartid # read current hart id
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bnez a0, park # if we're not on the hart 0
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#endif
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csrw SRC_XIE, 0 # clear Interrupt Registers
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csrw SRC_XIP, 0
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la t0, trap_entry
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csrw SRC_XTVEC, t0 # set Trap Vector Base Address Register
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/* set to disable FPU */
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li t0, XSTATUS_FS # close fpu
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csrc SRC_XSTATUS, t0
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#ifdef RISCV_S_MODE
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li t0, XSTATUS_PUM # PUM has no effect
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csrs SRC_XSTATUS, t0
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#endif
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.option push
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.option norelax
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la gp, __global_pointer$
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.option pop
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la sp, __stack_start__
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li t0, __STACKSIZE__
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add sp, sp, t0
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csrw SRC_XSCRATCH, sp
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j primary_cpu_entry
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park:
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wfi
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j park
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