c802fcdcf8
WCH CH569W-R0-1v0 evt board bsp port, first version dev/test under Ubuntu 20.04 toolchain from MounRiver_Studio_Community_Linux_x64_V120 tested drivers : SysTick, gpio, gpio interrupt, uart1 (RX interrupt, TX polling) libcpu/risc-v/SConscript : group includes rtconfig.CPU only if folder exists libcpu/risc-v/common/cpuport.c/rt_hw_context_switch_interrupt() : make it RT_WEAK for customization
29 lines
518 B
Python
29 lines
518 B
Python
from building import *
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cwd = GetCurrentDir()
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src = Split("""
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ch56x_sys.c
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swi_gcc.S
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""")
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if GetDepend('SOC_SERIES_CH569'):
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src += ['ch56x_pfic.c']
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if GetDepend('RT_USING_WDT'):
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src += ['ch56x_wdt.c']
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if GetDepend('RT_USING_HWTIMER'):
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src += ['ch56x_timer.c']
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if GetDepend('RT_USING_PIN'):
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src += ['ch56x_gpio.c']
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if GetDepend(['RT_USING_SERIAL', 'BSP_USING_UART']):
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src += ['ch56x_uart.c']
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path = [cwd]
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group = DefineGroup('Drivers', src, depend=[''], CPPPATH=path)
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Return('group')
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