893 lines
26 KiB
C
893 lines
26 KiB
C
/*
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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <errno.h>
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#include <typedef.h>
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#include <hal_mem.h>
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#include <sunxi_hal_geth.h>
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#include <lwip/pbuf.h>
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#include <netif/ethernet.h>
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#include <sunxi_hal_mii.h>
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#include <sunxi_hal_miiphy.h>
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#include <rtthread.h>
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#include <netif/ethernetif.h>
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#ifdef RT_USING_SMART
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#include <page.h>
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#include <ioremap.h>
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#endif
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#include <arch.h>
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static struct geth_device rt_geth_dev;
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static unsigned int rx_clean = 0;
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static int gmac_rx_desc_fill(rt_device_t dev)
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{
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unsigned int i = 0;
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unsigned int count = 0;
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hal_geth_dma_desc_t *rx_p = NULL;
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for(i=0; i<DMA_DESC_RX_NUM; i++)
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{
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rx_p = rt_geth_dev.get_buffer_config.dma_desc_rx + count;
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rx_p->desc0.rx.own = 1;
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rx_p->desc1.all |= ((1 << 11) - 1);
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count = circ_inc(count, DMA_DESC_RX_NUM);
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}
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count = 0;
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return 0;
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}
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void desc_buf_set(struct dma_desc *desc, unsigned long paddr, int size)
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{
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desc->desc1.all &= (~((1 << 11) - 1));
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desc->desc1.all |= (size & ((1 << 11) - 1));
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}
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void desc_set_own(struct dma_desc *desc)
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{
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desc->desc0.all |= 0x80000000;
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}
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void desc_tx_close(struct dma_desc *first, struct dma_desc *end, int csum_insert)
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{
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struct dma_desc *desc = first;
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first->desc1.tx.first_sg = 1;
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end->desc1.tx.last_seg = 1;
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end->desc1.tx.interrupt = 1;
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if (csum_insert)
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{
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do
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{
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desc->desc1.tx.cic = 3;
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desc++;
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} while (desc <= end);
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}
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}
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int desc_get_own(struct dma_desc *desc)
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{
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return desc->desc0.all & 0x80000000;
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}
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void desc_tag_clean(struct dma_desc *desc)
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{
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desc->resever0 = 0;
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}
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void desc_add_tag(struct dma_desc *desc)
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{
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desc->resever0 = 1;
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}
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static int geth_phy_read(char *devname, unsigned int phy_addr, unsigned char reg,unsigned short *data)
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{
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struct eth_device *dev;
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uint32_t value;
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value = geth_mdio_read(rt_geth_dev.iobase, phy_addr, reg);
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return value;
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}
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static int geth_phy_write(char *devname, unsigned int phy_addr, unsigned char reg, uint16_t data)
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{
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struct eth_device *dev;
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geth_mdio_write(rt_geth_dev.iobase, phy_addr, reg, data);
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return 0;
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}
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void geth_link_change(struct geth_device *dev,rt_bool_t up)
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{
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if(up)
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{
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printf("link up\n");
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eth_device_linkchange(&dev->parent, RT_TRUE);
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dev->phy_link_status = RT_TRUE;
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}
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else
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{
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printf("link down\n");
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eth_device_linkchange(&dev->parent, RT_FALSE);
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dev->phy_link_status = RT_FALSE;
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}
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}
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int read_data_from_eth(rt_device_t dev,struct pbuf *p,uint16_t *read_length)
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{
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unsigned int i = 0;
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int ret = -1;
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hal_geth_dma_desc_t *rx_p = NULL;
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unsigned int delay_count = 0;
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struct pbuf *q = NULL;
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int length = 0;
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int offset = 0;
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rx_p = rt_geth_dev.get_buffer_config.dma_desc_rx + rx_clean;
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awos_arch_mems_flush_dcache_region((unsigned long)rx_p,sizeof(hal_geth_dma_desc_t));
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awos_arch_mems_flush_dcache_region((unsigned long)rx_p->desc2,2048);
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dsb(v);
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if(!rx_p->desc0.rx.own)
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{
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length = rx_p->desc0.rx.frm_len;
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for(q = p;q != RT_NULL;q=q->next)
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{
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if((length - PBUF_MAX_BUFF_SIZE) <= 0)
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{
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rt_memcpy(q->payload,(void *)((unsigned long)rx_p->desc2 + offset),length);
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offset += length;
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break;
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}
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else
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{
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rt_memcpy(q->payload,(void *)((unsigned long)rx_p->desc2 + offset),PBUF_MAX_BUFF_SIZE);
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offset += PBUF_MAX_BUFF_SIZE;
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length -= PBUF_MAX_BUFF_SIZE;
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}
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}
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if(offset != (uint16_t)(rx_p->desc0.rx.frm_len))
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{
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*read_length = 0;
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ret = -1;
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printf("have not enough pbuf for receive data offset %d length %d\n",offset,length);
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}
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else
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{
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*read_length = offset;
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ret = 0;
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}
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rx_p->desc0.all = 0x80000000;
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awos_arch_mems_clean_dcache_region((unsigned long)rx_p,sizeof(hal_geth_dma_desc_t));
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rx_clean = circ_inc(rx_clean, DMA_DESC_RX_NUM);
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}
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else
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{
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read_length = 0;
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return -1;
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}
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return ret;
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}
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int tx_desc_recycle(rt_device_t dev)
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{
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struct dma_desc *desc;
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static int tx_clean = 0;
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desc = rt_geth_dev.get_buffer_config.dma_desc_tx + tx_clean;
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awos_arch_mems_flush_dcache_region((unsigned long)desc,sizeof(hal_geth_dma_desc_t));
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dsb(v);
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while((!desc_get_own(desc))&&(desc->resever0))
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{
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desc_tag_clean(desc);
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dsb(v);
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awos_arch_mems_clean_dcache_region((unsigned long)desc,sizeof(hal_geth_dma_desc_t));
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tx_clean = circ_inc(tx_clean, DMA_DESC_TX_NUM);
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desc = rt_geth_dev.get_buffer_config.dma_desc_tx + tx_clean;
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dsb(v);
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awos_arch_mems_flush_dcache_region((unsigned long)desc,sizeof(hal_geth_dma_desc_t));
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dsb(v);
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}
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return 0;
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}
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static irqreturn_t geth_irq_handler(int irq, void *dev_id)
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{
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int int_sta_value;
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int_sta_value = hal_readl(rt_geth_dev.iobase + GETH_INT_STA);
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int length;
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int ret = 0;
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if(RX_INT & int_sta_value)
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{
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hal_writel(RX_INT,rt_geth_dev.iobase + GETH_INT_STA);
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geth_rx_int_disable(rt_geth_dev.iobase);
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eth_device_ready(&(rt_geth_dev.parent));
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}
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if(TX_INT & int_sta_value)
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{
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hal_writel(RX_INT,rt_geth_dev.iobase + GETH_INT_STA);
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}
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/*clear all interrupt status*/
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hal_writel(int_sta_value,rt_geth_dev.iobase + GETH_INT_STA);
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return 0;
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}
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int is_enough_desc_available(struct dma_desc *entry)
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{
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struct pbuf *q = RT_NULL;
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struct dma_desc *desc;
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desc = entry;
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awos_arch_mems_flush_dcache_region((unsigned long)desc,sizeof(hal_geth_dma_desc_t));
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dsb(v);
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if(desc->desc0.tx.own != 0)
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{
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printf("desc %08x desc0 %08x desc1 %08x\n",desc,desc->desc0,desc->desc1);
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return RT_ERROR;
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}
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return RT_EOK;
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}
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int wait_tx_completed(struct dma_desc *entry)
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{
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struct pbuf *q = RT_NULL;
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struct dma_desc *desc;
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unsigned int timeout_cnt = 0;
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desc = entry;
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awos_arch_mems_flush_dcache_region((unsigned long)desc,sizeof(hal_geth_dma_desc_t));
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dsb(v);
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while(desc_get_own(desc))
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{
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awos_arch_mems_flush_dcache_region((unsigned long)desc,sizeof(hal_geth_dma_desc_t));
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dsb(v);
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timeout_cnt++;
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if(timeout_cnt > 1000)
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{
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printf("emac send data timeout \n");
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return RT_ERROR;
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}
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}
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desc_tag_clean(desc);
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dsb(v);
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awos_arch_mems_clean_dcache_region((unsigned long)desc,sizeof(hal_geth_dma_desc_t));
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return RT_EOK;
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}
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static rt_err_t rt_geth_xmit(rt_device_t dev, struct pbuf *p)
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{
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unsigned int entry;
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struct pbuf *q = RT_NULL;
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struct dma_desc *first, *paddr ,*end;
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static int tx_dirty = 0;
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static int tx_clean = 0;
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int desc_value = 0;
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void *dist = NULL;
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int ret = 0;
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unsigned int i = 0;
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unsigned int copy_offset = 0;
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if (!rt_geth_dev.phy_link_status) return RT_ERROR;
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first = rt_geth_dev.get_buffer_config.dma_desc_tx + tx_dirty;
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ret = is_enough_desc_available(first);
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if(ret < 0)
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{
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return RT_ERROR;
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}
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copy_offset = 0;
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for(q = p;q != RT_NULL;q=q->next)
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{
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dist = (void *)((unsigned long)first->desc2);
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rt_memcpy(dist+copy_offset,q->payload,q->len);
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copy_offset += q->len;
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if(copy_offset >= ((1 << 11) - 1))
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{
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printf("send data exceed max len copy_offset %d\n",copy_offset);
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return RT_ERROR;
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}
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}
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desc_buf_set(first, 0, copy_offset);
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desc_add_tag(first);
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tx_dirty = circ_inc(tx_dirty, DMA_DESC_TX_NUM);
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end = first;
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desc_set_own(first);
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desc_tx_close(first, end, 0);
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dsb(v);
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awos_arch_mems_clean_dcache_region((unsigned long)first,sizeof(hal_geth_dma_desc_t));
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awos_arch_mems_clean_dcache_region((unsigned long)first->desc2,copy_offset);
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dsb(v);
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/* Enable transmit and Poll transmit */
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geth_tx_poll(rt_geth_dev.iobase);
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ret = wait_tx_completed(first);
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return ret;
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}
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static struct pbuf *rt_geth_recv(rt_device_t dev)
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{
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static struct pbuf *p_s = RT_NULL;
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struct pbuf *p = RT_NULL;
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int status;
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uint16_t length = 0;
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static int first_flag = 0;
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uint64_t before_get_data_tick;
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uint64_t diff_tick0;
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uint64_t diff_tick1;
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uint64_t diff_tick2;
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if(p_s == RT_NULL)
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{
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p_s = pbuf_alloc(PBUF_RAW, ENET_FRAME_MAX_FRAMELEN, PBUF_POOL);
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if(p_s == RT_NULL)
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{
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return RT_NULL;
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}
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}
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p = p_s;
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status = read_data_from_eth(dev,p,&length);
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if(status == -1)
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{
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geth_rx_int_enable(rt_geth_dev.iobase);
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return NULL;
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}
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pbuf_realloc(p, length);
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p_s = RT_NULL;
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return p;
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}
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static int rx_status(hal_geth_dma_desc_t *p)
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{
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int ret = good_frame;
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if (p->desc0.rx.last_desc == 0)
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ret = discard_frame;
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if (p->desc0.rx.frm_type && (p->desc0.rx.chsum_err
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|| p->desc0.rx.ipch_err))
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ret = discard_frame;
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if (p->desc0.rx.err_sum)
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ret = discard_frame;
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if (p->desc0.rx.len_err)
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ret = discard_frame;
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if (p->desc0.rx.mii_err)
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ret = discard_frame;
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return ret;
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}
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static void geth_set_hwaddr(unsigned char *addr)
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{
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geth_set_mac_addr(rt_geth_dev.iobase, addr, 0);
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}
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static void geth_get_hwaddr(struct eth_device *dev)
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{
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}
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/********************************************************
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RGMII RMI D1 F133
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---------------------------------------------------------
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RXD3 / PE14 PG9 / PG9
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RXD2 / PE13 PG8 PE13 PG8
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RXD1 RXD1 PE2 PG2 PE2 PG2
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RXD0 RXD0 PE1 PG1 PE1 PG1
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RXCK / PE15 PG10 / PG10
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RXCTRL CRS-DV PE0 PG0 PE0 PG0
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TXD3 / PE12 PG7 PE12 PG7
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TXD2 / PE11 PG6 PE11 PG6
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TXD1 TXD1 PE5 PG5 PE5 PG5
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TXD0 TXD0 PE4 PG4 PE4 PG4
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TXCK TXCK PE3 PG3 PE3 PG3
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TXCTL TXEN PE6 PG12 PE6 PG12
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CLKIN RXER PE7 PG13 PE7 PG13
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MDC MDC PE8 PG14 PE8 PG14
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MDIO MDIO PE9 PG15 PE9 PG15
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EPHY-25M EPHY-25M PE10 PG11 PE10 PG11
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*/
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static void geth_pinctrl_init(void)
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{
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#ifdef GMAC_USING_GPIOE
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hal_gpio_pinmux_set_function(GPIO_PE0, 8);
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hal_gpio_pinmux_set_function(GPIO_PE1, 8);
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hal_gpio_pinmux_set_function(GPIO_PE2, 8);
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hal_gpio_pinmux_set_function(GPIO_PE3, 8);
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hal_gpio_pinmux_set_function(GPIO_PE4, 8);
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hal_gpio_pinmux_set_function(GPIO_PE5, 8);
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hal_gpio_pinmux_set_function(GPIO_PE6, 8);
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hal_gpio_pinmux_set_function(GPIO_PE7, 8);
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hal_gpio_pinmux_set_function(GPIO_PE8, 8);
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hal_gpio_pinmux_set_function(GPIO_PE9, 8);
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hal_gpio_pinmux_set_function(GPIO_PE10, 8);
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#ifdef GMAC_USING_RGMII
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hal_gpio_pinmux_set_function(GPIO_PE11, 8);
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hal_gpio_pinmux_set_function(GPIO_PE12, 8);
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hal_gpio_pinmux_set_function(GPIO_PE13, 8);
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#ifdef BOARD_allwinnerd1
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hal_gpio_pinmux_set_function(GPIO_PE14, 8);
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hal_gpio_pinmux_set_function(GPIO_PE15, 8);
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#endif /* BOARD_allwinnerd1 */
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#ifdef BOARD_allwinnerd1s
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hal_gpio_pinmux_set_function(GPIO_PG9, 4);
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hal_gpio_pinmux_set_function(GPIO_PG10, 4);
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#endif /* BOARD_allwinnerd1s */
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#endif /* GMAC_USING_RGMII */
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#endif /* GMAC_USING_GPIOE */
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#ifdef GMAC_USING_GPIOG
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hal_gpio_pinmux_set_function(GPIO_PG0, 4);
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hal_gpio_pinmux_set_function(GPIO_PG1, 4);
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hal_gpio_pinmux_set_function(GPIO_PG2, 4);
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hal_gpio_pinmux_set_function(GPIO_PG3, 4);
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hal_gpio_pinmux_set_function(GPIO_PG4, 4);
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hal_gpio_pinmux_set_function(GPIO_PG5, 4);
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#ifdef GMAC_USING_RGMII
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hal_gpio_pinmux_set_function(GPIO_PG6, 4);
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hal_gpio_pinmux_set_function(GPIO_PG7, 4);
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hal_gpio_pinmux_set_function(GPIO_PG8, 4);
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hal_gpio_pinmux_set_function(GPIO_PG9, 4);
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hal_gpio_pinmux_set_function(GPIO_PG10, 4);
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#endif /* GMAC_USING_RGMII */
|
||
hal_gpio_pinmux_set_function(GPIO_PG11, 4);
|
||
hal_gpio_pinmux_set_function(GPIO_PG12, 4);
|
||
hal_gpio_pinmux_set_function(GPIO_PG13, 4);
|
||
hal_gpio_pinmux_set_function(GPIO_PE14, 4);
|
||
hal_gpio_pinmux_set_function(GPIO_PE15, 4);
|
||
#endif /* GMAC_USING_GPIOG */
|
||
}
|
||
|
||
static int geth_phy_init(struct eth_device *dev)
|
||
{
|
||
uint32_t value;
|
||
uint16_t phy_val;
|
||
int i;
|
||
uint32_t phy_addr = 0x1f;
|
||
int duplex;
|
||
int speed;
|
||
uint16_t temp = 0;
|
||
|
||
for (i = 0; i < 0x1f; i++) {
|
||
value = (geth_phy_read((char *)dev, i, MII_PHYSID1,NULL)
|
||
& 0xffff) << 16;
|
||
value |= (geth_phy_read((char *)dev, i, MII_PHYSID2,NULL) & 0xffff);
|
||
|
||
if ((value & 0x1fffffff) == 0x1fffffff) {
|
||
rt_thread_delay(RT_TICK_PER_SECOND/100);
|
||
continue;
|
||
}
|
||
phy_addr = i;
|
||
break;
|
||
}
|
||
|
||
phy_addr = i;
|
||
if (phy_addr == 0x1f) {
|
||
printf("No PHY device!\n");
|
||
return -1;
|
||
}
|
||
phy_val = geth_phy_read((char *)dev, phy_addr, MII_BMCR,NULL);
|
||
geth_phy_write((char *)dev, phy_addr, MII_BMCR, phy_val | BMCR_RESET);
|
||
while (geth_phy_read((char *)dev, phy_addr, MII_BMCR,NULL) & BMCR_RESET);
|
||
|
||
phy_val = geth_phy_read((char *)dev, phy_addr, MII_BMCR,NULL);
|
||
geth_phy_write((char *)dev, phy_addr, MII_BMCR, phy_val | BMCR_FULLDPLX);
|
||
|
||
/* Reset phy chip */
|
||
phy_val = geth_phy_read((char *)dev, phy_addr, MII_BMCR,NULL);
|
||
geth_phy_write((char *)dev, phy_addr, MII_BMCR, (phy_val & ~BMCR_PDOWN));
|
||
while (geth_phy_read((char *)dev, phy_addr, MII_BMCR,NULL) & BMCR_PDOWN);
|
||
|
||
/* Wait BMSR_ANEGCOMPLETE be set */
|
||
while (!(geth_phy_read((char *)dev, phy_addr, MII_BMSR,NULL) & BMSR_ANEGCOMPLETE)) {
|
||
if (i > 40) {
|
||
printf("Warning: Auto negotiation timeout!\n");
|
||
return -1;
|
||
}
|
||
rt_thread_delay(RT_TICK_PER_SECOND/2);
|
||
i++;
|
||
}
|
||
|
||
phy_val = geth_phy_read((char *)dev, phy_addr, MII_RESV2,NULL);
|
||
temp = (phy_val>>4) & 0x3;
|
||
switch(temp)
|
||
{
|
||
case 2:
|
||
speed = 1000;
|
||
break;
|
||
case 1:
|
||
speed = 100;
|
||
break;
|
||
case 0:
|
||
speed = 10;
|
||
break;
|
||
default :
|
||
break;
|
||
}
|
||
temp = phy_val & 0x08;
|
||
duplex = (temp) ? 1 : 0;
|
||
geth_set_link_mode(rt_geth_dev.iobase,duplex,speed);
|
||
|
||
return 0;
|
||
}
|
||
|
||
static int geth_dma_desc_init(void)
|
||
{
|
||
void *temp = RT_NULL;
|
||
|
||
#ifdef RT_USING_SMART
|
||
rt_geth_dev.get_buffer_config.rx_buff_addr = rt_pages_alloc(RX_BUFFER_INDEX_NUM);
|
||
#else
|
||
rt_geth_dev.get_buffer_config.rx_buff_addr = rt_malloc(DMA_MEM_ALIGN_SIZE * DMA_DESC_RX_NUM);
|
||
#endif
|
||
if(!rt_geth_dev.get_buffer_config.rx_buff_addr)
|
||
{
|
||
printf("ERROR: rx buff page alloc failed\n");
|
||
return -1;
|
||
}
|
||
//temp = (void *)rt_ioremap_nocache((void *)awos_arch_virt_to_phys((unsigned long)rt_geth_dev.get_buffer_config.rx_buff_addr), (SYS_PAGE_SIZE<<RX_BUFFER_INDEX_NUM));
|
||
rt_geth_dev.get_buffer_config.phy_rx_buff_addr = (void *)awos_arch_virt_to_phys((unsigned long)rt_geth_dev.get_buffer_config.rx_buff_addr);
|
||
#ifdef RT_USING_SMART
|
||
rt_geth_dev.get_buffer_config.tx_buff_addr = rt_pages_alloc(TX_BUFFER_INDEX_NUM);
|
||
#else
|
||
rt_geth_dev.get_buffer_config.tx_buff_addr = rt_malloc(DMA_MEM_ALIGN_SIZE * DMA_DESC_TX_NUM);
|
||
#endif
|
||
if(!rt_geth_dev.get_buffer_config.tx_buff_addr)
|
||
{
|
||
printf("ERROR: tx buff page alloc failed\n");
|
||
return -1;
|
||
}
|
||
//temp = (void *)rt_ioremap_nocache((void *)awos_arch_virt_to_phys((unsigned long)rt_geth_dev.get_buffer_config.tx_buff_addr), (SYS_PAGE_SIZE<<TX_BUFFER_INDEX_NUM));
|
||
rt_geth_dev.get_buffer_config.phy_tx_buff_addr = (void *)awos_arch_virt_to_phys((unsigned long)rt_geth_dev.get_buffer_config.tx_buff_addr);
|
||
|
||
#ifdef RT_USING_SMART
|
||
rt_geth_dev.get_buffer_config.dma_desc_rx = (hal_geth_dma_desc_t *)rt_pages_alloc(RX_BD_INDEX_NUM);
|
||
#else
|
||
rt_geth_dev.get_buffer_config.dma_desc_rx = (hal_geth_dma_desc_t *)rt_malloc(sizeof(hal_geth_dma_desc_t) * DMA_DESC_RX_NUM);
|
||
#endif
|
||
if(!rt_geth_dev.get_buffer_config.dma_desc_rx)
|
||
{
|
||
printf("ERROR: rx bd page alloc failed\n");
|
||
return -1;
|
||
}
|
||
|
||
//temp = (void *)rt_ioremap_nocache((void *)awos_arch_virt_to_phys((unsigned long)rt_geth_dev.get_buffer_config.dma_desc_rx), (SYS_PAGE_SIZE<<RX_BD_INDEX_NUM));
|
||
rt_geth_dev.get_buffer_config.phy_dma_desc_rx = (hal_geth_dma_desc_t *)awos_arch_virt_to_phys((unsigned long)rt_geth_dev.get_buffer_config.dma_desc_rx);
|
||
#ifdef RT_USING_SMART
|
||
rt_geth_dev.get_buffer_config.dma_desc_tx = (hal_geth_dma_desc_t *)rt_pages_alloc(TX_BD_INDEX_NUM);
|
||
#else
|
||
rt_geth_dev.get_buffer_config.dma_desc_tx = (hal_geth_dma_desc_t *)rt_malloc(sizeof(hal_geth_dma_desc_t) * DMA_DESC_TX_NUM);
|
||
#endif
|
||
if(!rt_geth_dev.get_buffer_config.dma_desc_tx)
|
||
{
|
||
printf("ERROR: tx bd page alloc failed\n");
|
||
return -1;
|
||
}
|
||
//temp = (void *)rt_ioremap_nocache((void *)awos_arch_virt_to_phys((unsigned long)rt_geth_dev.get_buffer_config.dma_desc_tx), (SYS_PAGE_SIZE<<TX_BD_INDEX_NUM));
|
||
rt_geth_dev.get_buffer_config.phy_dma_desc_tx = (hal_geth_dma_desc_t *)awos_arch_virt_to_phys((unsigned long)rt_geth_dev.get_buffer_config.dma_desc_tx);
|
||
|
||
return 0;
|
||
}
|
||
|
||
void desc_init_chain(hal_geth_dma_desc_t *desc, unsigned long addr, unsigned long first_buff_addr,unsigned int size,unsigned int align_size)
|
||
{
|
||
/* In chained mode the desc3 points to the next element in the ring.
|
||
* The latest element has to point to the head.
|
||
*/
|
||
int i;
|
||
hal_geth_dma_desc_t *p = desc;
|
||
unsigned long dma_desc_phy = addr;
|
||
unsigned long dma_buff_phy = first_buff_addr;
|
||
|
||
for (i = 0; i < size; i++) {
|
||
|
||
if(i == (size - 1))
|
||
{
|
||
p->desc2 = (u32)dma_buff_phy;
|
||
p->desc3 = (u32)addr;
|
||
}
|
||
else
|
||
{
|
||
dma_desc_phy += sizeof(hal_geth_dma_desc_t);
|
||
p->desc2 = (u32)dma_buff_phy;
|
||
p->desc3 = (u32)dma_desc_phy;
|
||
p++;
|
||
}
|
||
dma_buff_phy += align_size;
|
||
}
|
||
}
|
||
|
||
static rt_err_t rt_geth_init(rt_device_t dev)
|
||
{
|
||
uint32_t value;
|
||
|
||
/* Enable clock */
|
||
|
||
uint32_t used_type = rt_geth_dev.used_type;
|
||
uint32_t tx_delay = rt_geth_dev.tx_delay;
|
||
uint32_t rx_delay = rt_geth_dev.rx_delay;
|
||
uint32_t phy_interface = rt_geth_dev.phy_interface;
|
||
geth_clk_enable(used_type,phy_interface,tx_delay,rx_delay);
|
||
|
||
/* Pinctrl init */
|
||
geth_pinctrl_init();
|
||
/* MAC controller soft reset */
|
||
value = geth_mac_reset(rt_geth_dev.iobase);
|
||
if (!value)
|
||
{
|
||
printf("Gmac controller softs reset success\n");
|
||
}
|
||
else
|
||
{
|
||
printf("Gmac controller soft reset failed value %08x\n",value);
|
||
}
|
||
/* MAC controller initialize */
|
||
geth_mac_init(rt_geth_dev.iobase);
|
||
|
||
geth_set_hwaddr(rt_geth_dev.dev_addr);
|
||
/* Frame filter */
|
||
geth_set_filter(rt_geth_dev.iobase);
|
||
/* Burst should be 8 */
|
||
value = hal_readl(rt_geth_dev.iobase + GETH_BASIC_CTL1);
|
||
value |= (8 << 24);
|
||
hal_writel(value, rt_geth_dev.iobase + GETH_BASIC_CTL1);
|
||
|
||
/* Disable all interrupt of dma */
|
||
geth_all_int_disable(rt_geth_dev.iobase);
|
||
|
||
value = geth_dma_desc_init();
|
||
if(value < 0) {
|
||
printf("Gmac dma desc init fail!\n");
|
||
return -1;
|
||
}
|
||
|
||
memset((void *)rt_geth_dev.get_buffer_config.dma_desc_tx, 0, sizeof(hal_geth_dma_desc_t)*DMA_DESC_TX_NUM);
|
||
memset((void *)rt_geth_dev.get_buffer_config.dma_desc_rx, 0, sizeof(hal_geth_dma_desc_t)*DMA_DESC_RX_NUM);
|
||
|
||
desc_init_chain(rt_geth_dev.get_buffer_config.dma_desc_tx, (unsigned long)rt_geth_dev.get_buffer_config.phy_dma_desc_tx,
|
||
(unsigned long)rt_geth_dev.get_buffer_config.phy_tx_buff_addr, DMA_DESC_TX_NUM, DMA_MEM_ALIGN_SIZE);
|
||
desc_init_chain(rt_geth_dev.get_buffer_config.dma_desc_rx, (unsigned long)rt_geth_dev.get_buffer_config.phy_dma_desc_rx,
|
||
(unsigned long)rt_geth_dev.get_buffer_config.phy_rx_buff_addr, DMA_DESC_RX_NUM, DMA_MEM_ALIGN_SIZE);
|
||
|
||
gmac_rx_desc_fill(NULL);
|
||
|
||
hal_writel((unsigned long)rt_geth_dev.get_buffer_config.dma_desc_tx, rt_geth_dev.iobase + GETH_TX_DESC_LIST);
|
||
hal_writel((unsigned long)rt_geth_dev.get_buffer_config.dma_desc_rx, rt_geth_dev.iobase + GETH_RX_DESC_LIST);
|
||
|
||
awos_arch_mems_clean_dcache_region((unsigned long)rt_geth_dev.get_buffer_config.dma_desc_tx, sizeof(hal_geth_dma_desc_t)*DMA_DESC_TX_NUM);
|
||
awos_arch_mems_clean_dcache_region((unsigned long)rt_geth_dev.get_buffer_config.dma_desc_rx, sizeof(hal_geth_dma_desc_t)*DMA_DESC_RX_NUM);
|
||
dsb(v);
|
||
/* start tx & rx */
|
||
geth_start_tx(rt_geth_dev.iobase);
|
||
geth_start_rx(rt_geth_dev.iobase);
|
||
|
||
/* Enable transmit & receive */
|
||
geth_mac_enable(rt_geth_dev.iobase);
|
||
|
||
if (request_irq(GETH_IRQ_NUM, geth_irq_handler, 0, "geth", (void *)&rt_geth_dev) < 0)
|
||
{
|
||
printf("request irq error\n");
|
||
return -1;
|
||
}
|
||
|
||
enable_irq(GETH_IRQ_NUM);
|
||
geth_rx_int_enable(rt_geth_dev.iobase);
|
||
return 0;
|
||
}
|
||
|
||
static void rt_geth_uninitialize(rt_device_t dev)
|
||
{
|
||
geth_mac_disable(rt_geth_dev.iobase);
|
||
geth_clk_disable();
|
||
}
|
||
|
||
static rt_err_t rt_geth_open(rt_device_t dev, rt_uint16_t oflag)
|
||
{
|
||
printf("gmac open\n");
|
||
return RT_EOK;
|
||
}
|
||
|
||
static rt_err_t rt_geth_close(rt_device_t dev)
|
||
{
|
||
printf("gmac close\n");
|
||
return RT_EOK;
|
||
}
|
||
|
||
static rt_ssize_t rt_geth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
|
||
{
|
||
printf("gmac read\n");
|
||
rt_set_errno(-RT_ENOSYS);
|
||
return 0;
|
||
}
|
||
|
||
static rt_ssize_t rt_geth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
|
||
{
|
||
printf("gmac write\n");
|
||
rt_set_errno(-RT_ENOSYS);
|
||
return 0;
|
||
}
|
||
|
||
static rt_err_t rt_geth_control(rt_device_t dev, int cmd, void *args)
|
||
{
|
||
switch(cmd)
|
||
{
|
||
case NIOCTL_GADDR:
|
||
/* get mac address */
|
||
if(args) {
|
||
rt_memcpy(args, rt_geth_dev.dev_addr, 6);
|
||
} else {
|
||
return -RT_ERROR;
|
||
}
|
||
break;
|
||
|
||
default :
|
||
break;
|
||
}
|
||
|
||
return RT_EOK;
|
||
}
|
||
int is_data_availabl()
|
||
{
|
||
|
||
hal_geth_dma_desc_t *rx_p = NULL;
|
||
rx_p = rt_geth_dev.get_buffer_config.dma_desc_rx + rx_clean;
|
||
|
||
awos_arch_mems_flush_dcache_region((unsigned long)rx_p,sizeof(hal_geth_dma_desc_t));
|
||
awos_arch_mems_flush_dcache_region((unsigned long)rx_p->desc2,2048);
|
||
dsb(v);
|
||
|
||
if(!rx_p->desc0.rx.own)
|
||
{
|
||
if((rx_p->desc0.rx.last_desc != 1)||(rx_p->desc0.rx.first_desc != 1))
|
||
{
|
||
printf("first %d last %d\n",rx_p->desc0.rx.first_desc,rx_p->desc0.rx.last_desc);
|
||
}
|
||
return 0;
|
||
}
|
||
else
|
||
{
|
||
return -1;
|
||
}
|
||
|
||
return 0;
|
||
}
|
||
|
||
static void phy_link_detect(void *param)
|
||
{
|
||
|
||
uint16_t bmsr = 0;
|
||
uint16_t link_status = 0;
|
||
uint16_t link_status_old = 0;
|
||
uint16_t phy_val;
|
||
int ret = -1;
|
||
|
||
while(1)
|
||
{
|
||
bmsr = geth_phy_read(NULL, 0, MII_BMSR,NULL);
|
||
link_status = bmsr & BMSR_LSTATUS;
|
||
if(link_status_old != link_status)
|
||
{
|
||
if(link_status)
|
||
{
|
||
ret = geth_phy_init((struct eth_device *)param);
|
||
if(ret == 0)
|
||
{
|
||
geth_link_change(&rt_geth_dev,1);
|
||
}
|
||
}
|
||
else
|
||
{
|
||
if(link_status_old != link_status)
|
||
{
|
||
geth_link_change(&rt_geth_dev,0);
|
||
}
|
||
}
|
||
|
||
}
|
||
link_status_old = link_status;
|
||
rt_thread_delay(RT_TICK_PER_SECOND);
|
||
}
|
||
|
||
}
|
||
void rt_geth_driver_init(void)
|
||
{
|
||
rt_err_t state = RT_EOK;
|
||
|
||
rt_geth_dev.iobase = IOBASE;
|
||
rt_geth_dev.phy_interface = PHY_INTERFACE_MODE_RGMII;
|
||
rt_geth_dev.used_type = EXT_PHY;
|
||
rt_geth_dev.tx_delay = 3;
|
||
rt_geth_dev.rx_delay = 0;
|
||
|
||
random_ether_addr(rt_geth_dev.dev_addr);
|
||
rt_geth_dev.parent.parent.init = rt_geth_init;
|
||
rt_geth_dev.parent.parent.open = rt_geth_open;
|
||
rt_geth_dev.parent.parent.close = rt_geth_close;
|
||
rt_geth_dev.parent.parent.read = rt_geth_read;
|
||
rt_geth_dev.parent.parent.write = rt_geth_write;
|
||
rt_geth_dev.parent.parent.control = rt_geth_control;
|
||
rt_geth_dev.parent.parent.user_data = RT_NULL;
|
||
|
||
rt_geth_dev.parent.eth_rx = rt_geth_recv;
|
||
rt_geth_dev.parent.eth_tx = rt_geth_xmit;
|
||
/* register eth device */
|
||
state = eth_device_init(&(rt_geth_dev.parent), "e0");
|
||
if (RT_EOK == state) {
|
||
printf("gmac device init success\n");
|
||
} else {
|
||
printf("gmac device init failed: %d\n", state);
|
||
}
|
||
|
||
rt_thread_t link_detect;
|
||
link_detect = rt_thread_create("link_detect",
|
||
phy_link_detect,
|
||
(void *)&rt_geth_dev,
|
||
4096,
|
||
13,
|
||
2);
|
||
if (link_detect != RT_NULL)
|
||
{
|
||
rt_thread_startup(link_detect);
|
||
}
|
||
|
||
return;
|
||
}
|
||
|
||
static int rt_hw_eth_drvier_init(void)
|
||
{
|
||
rt_geth_driver_init();
|
||
|
||
return 0;
|
||
}
|
||
INIT_DEVICE_EXPORT(rt_hw_eth_drvier_init);
|