468 lines
14 KiB
C
468 lines
14 KiB
C
#include <rthw.h>
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <drivers/mmcsd_core.h>
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#include <stdint.h>
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#include <stdio.h>
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#include "drv_sdio.h"
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#ifdef RT_USING_SDIO
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#define MMC_BASE_ADDR (0x10005000)
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#define PL180_POWER (0x00)
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#define PL180_CLOCK (0x04)
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#define PL180_ARGUMENT (0x08)
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#define PL180_COMMAND (0x0c)
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#define PL180_RESPCMD (0x10)
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#define PL180_RESP0 (0x14)
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#define PL180_RESP1 (0x18)
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#define PL180_RESP2 (0x1c)
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#define PL180_RESP3 (0x20)
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#define PL180_DATA_TIMER (0x24)
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#define PL180_DATA_LENGTH (0x28)
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#define PL180_DATA_CTRL (0x2c)
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#define PL180_DATA_CNT (0x30)
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#define PL180_STATUS (0x34)
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#define PL180_CLEAR (0x38)
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#define PL180_MASK0 (0x3c)
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#define PL180_MASK1 (0x40)
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#define PL180_SELECT (0x44)
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#define PL180_FIFO_CNT (0x48)
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#define PL180_FIFO (0x80)
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#define PL180_RSP_NONE (0 << 0)
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#define PL180_RSP_PRESENT (1 << 0)
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#define PL180_RSP_136BIT (1 << 1)
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#define PL180_RSP_CRC (1 << 2)
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#define PL180_CMD_WAITRESP (1 << 6)
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#define PL180_CMD_LONGRSP (1 << 7)
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#define PL180_CMD_WAITINT (1 << 8)
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#define PL180_CMD_WAITPEND (1 << 9)
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#define PL180_CMD_ENABLE (1 << 10)
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#define PL180_STAT_CMD_CRC_FAIL (1 << 0)
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#define PL180_STAT_DAT_CRC_FAIL (1 << 1)
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#define PL180_STAT_CMD_TIME_OUT (1 << 2)
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#define PL180_STAT_DAT_TIME_OUT (1 << 3)
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#define PL180_STAT_TX_UNDERRUN (1 << 4)
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#define PL180_STAT_RX_OVERRUN (1 << 5)
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#define PL180_STAT_CMD_RESP_END (1 << 6)
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#define PL180_STAT_CMD_SENT (1 << 7)
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#define PL180_STAT_DAT_END (1 << 8)
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#define PL180_STAT_DAT_BLK_END (1 << 10)
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#define PL180_STAT_CMD_ACT (1 << 11)
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#define PL180_STAT_TX_ACT (1 << 12)
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#define PL180_STAT_RX_ACT (1 << 13)
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#define PL180_STAT_TX_FIFO_HALF (1 << 14)
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#define PL180_STAT_RX_FIFO_HALF (1 << 15)
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#define PL180_STAT_TX_FIFO_FULL (1 << 16)
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#define PL180_STAT_RX_FIFO_FULL (1 << 17)
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#define PL180_STAT_TX_FIFO_ZERO (1 << 18)
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#define PL180_STAT_RX_DAT_ZERO (1 << 19)
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#define PL180_STAT_TX_DAT_AVL (1 << 20)
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#define PL180_STAT_RX_FIFO_AVL (1 << 21)
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#define PL180_CLR_CMD_CRC_FAIL (1 << 0)
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#define PL180_CLR_DAT_CRC_FAIL (1 << 1)
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#define PL180_CLR_CMD_TIMEOUT (1 << 2)
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#define PL180_CLR_DAT_TIMEOUT (1 << 3)
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#define PL180_CLR_TX_UNDERRUN (1 << 4)
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#define PL180_CLR_RX_OVERRUN (1 << 5)
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#define PL180_CLR_CMD_RESP_END (1 << 6)
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#define PL180_CLR_CMD_SENT (1 << 7)
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#define PL180_CLR_DAT_END (1 << 8)
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#define PL180_CLR_DAT_BLK_END (1 << 10)
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#define DBG_TAG "drv.sdio"
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#define DBG_LVL DBG_INFO
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#include "rtdbg.h"
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struct sdhci_pl180_pdata_t
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{
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rt_uint32_t virt;
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};
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static inline rt_uint32_t read32(uint32_t addr)
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{
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return( *((volatile rt_uint32_t *)(addr)) );
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}
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static inline void write32(uint32_t addr, rt_uint32_t value)
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{
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*((volatile rt_uint32_t *)(addr)) = value;
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}
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static rt_err_t pl180_transfer_command(struct sdhci_pl180_pdata_t * pdat, struct sdhci_cmd_t * cmd)
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{
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rt_uint32_t cmdidx;
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rt_uint32_t status;
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rt_err_t ret = RT_EOK;
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if(read32(pdat->virt + PL180_COMMAND) & PL180_CMD_ENABLE)
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write32(pdat->virt + PL180_COMMAND, 0x0);
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cmdidx = (cmd->cmdidx & 0xff) | PL180_CMD_ENABLE;
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if(cmd->resptype)
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{
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cmdidx |= PL180_CMD_WAITRESP;
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if(cmd->resptype & PL180_RSP_136BIT)
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cmdidx |= PL180_CMD_LONGRSP;
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}
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write32(pdat->virt + PL180_ARGUMENT, cmd->cmdarg);
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write32(pdat->virt + PL180_COMMAND, cmdidx);
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do {
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status = read32(pdat->virt + PL180_STATUS);
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} while(!(status & (PL180_STAT_CMD_SENT | PL180_STAT_CMD_RESP_END | PL180_STAT_CMD_TIME_OUT | PL180_STAT_CMD_CRC_FAIL)));
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LOG_D("mmc status done!");
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if(cmd->resptype & PL180_RSP_PRESENT)
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{
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cmd->response[0] = read32(pdat->virt + PL180_RESP0);
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if(cmd->resptype & PL180_RSP_136BIT)
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{
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LOG_D("136bit response");
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cmd->response[1] = read32(pdat->virt + PL180_RESP1);
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cmd->response[2] = read32(pdat->virt + PL180_RESP2);
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cmd->response[3] = read32(pdat->virt + PL180_RESP3);
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}
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}
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if(status & PL180_STAT_CMD_TIME_OUT)
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{
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ret = -RT_ETIMEOUT;
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}
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else if ((status & PL180_STAT_CMD_CRC_FAIL) && (cmd->resptype & PL180_RSP_CRC))
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{
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ret = -RT_ERROR;
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}
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write32(pdat->virt + PL180_CLEAR, (PL180_CLR_CMD_SENT | PL180_CLR_CMD_RESP_END | PL180_CLR_CMD_TIMEOUT | PL180_CLR_CMD_CRC_FAIL));
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return ret;
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}
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static rt_err_t read_bytes(struct sdhci_pl180_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize)
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{
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rt_uint32_t * tmp = buf;
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rt_uint32_t count = blkcount * blksize;
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rt_uint32_t status, err;
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status = read32(pdat->virt + PL180_STATUS);
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err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_RX_OVERRUN);
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while((!err) && (count >= sizeof(rt_uint32_t)))
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{
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if(status & PL180_STAT_RX_FIFO_AVL)
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{
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*(tmp) = read32(pdat->virt + PL180_FIFO);
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tmp++;
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count -= sizeof(rt_uint32_t);
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}
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status = read32(pdat->virt + PL180_STATUS);
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err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_RX_OVERRUN);
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}
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err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END | PL180_STAT_RX_OVERRUN);
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while(!err)
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{
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status = read32(pdat->virt + PL180_STATUS);
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err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END | PL180_STAT_RX_OVERRUN);
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}
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if(status & PL180_STAT_DAT_TIME_OUT)
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return -RT_ERROR;
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else if (status & PL180_STAT_DAT_CRC_FAIL)
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return -RT_ERROR;
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else if (status & PL180_STAT_RX_OVERRUN)
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return -RT_ERROR;
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write32(pdat->virt + PL180_CLEAR, 0x1DC007FF);
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if(count)
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return -RT_ERROR;
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return RT_EOK;
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}
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static rt_err_t write_bytes(struct sdhci_pl180_pdata_t * pdat, rt_uint32_t * buf, rt_uint32_t blkcount, rt_uint32_t blksize)
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{
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rt_uint32_t * tmp = buf;
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rt_uint32_t count = blkcount * blksize;
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rt_uint32_t status, err;
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int i;
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status = read32(pdat->virt + PL180_STATUS);
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err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT);
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while(!err && count)
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{
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if(status & PL180_STAT_TX_FIFO_HALF)
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{
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if(count >= 8 * sizeof(rt_uint32_t))
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{
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for(i = 0; i < 8; i++)
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write32(pdat->virt + PL180_FIFO, *(tmp + i));
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tmp += 8;
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count -= 8 * sizeof(rt_uint32_t);
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}
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else
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{
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while(count >= sizeof(rt_uint32_t))
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{
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write32(pdat->virt + PL180_FIFO, *tmp);
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tmp++;
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count -= sizeof(rt_uint32_t);
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}
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}
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}
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status = read32(pdat->virt + PL180_STATUS);
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err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT);
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}
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err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END);
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while(!err)
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{
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status = read32(pdat->virt + PL180_STATUS);
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err = status & (PL180_STAT_DAT_CRC_FAIL | PL180_STAT_DAT_TIME_OUT | PL180_STAT_DAT_BLK_END);
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}
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if(status & PL180_STAT_DAT_TIME_OUT)
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return -RT_ERROR;
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else if (status & PL180_STAT_DAT_CRC_FAIL)
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return -RT_ERROR;
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write32(pdat->virt + PL180_CLEAR, 0x1DC007FF);
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if(count)
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return -RT_ERROR;
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return RT_EOK;
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}
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static rt_err_t pl180_transfer_data(struct sdhci_pl180_pdata_t * pdat, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat)
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{
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rt_uint32_t dlen = (rt_uint32_t)(dat->blkcnt * dat->blksz);
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rt_uint32_t blksz_bits = dat->blksz - 1;
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rt_uint32_t dctrl = (blksz_bits << 4) | (0x1 << 0) | (0x1 << 14);
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rt_err_t ret = -RT_ERROR;
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write32(pdat->virt + PL180_DATA_TIMER, 0xffff);
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write32(pdat->virt + PL180_DATA_LENGTH, dlen);
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if(dat->flag & DATA_DIR_READ)
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{
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dctrl |= (0x1 << 1);
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write32(pdat->virt + PL180_DATA_CTRL, dctrl);
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ret = pl180_transfer_command(pdat, cmd);
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if (ret < 0) return ret;
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ret = read_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz);
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}
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else if(dat->flag & DATA_DIR_WRITE)
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{
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ret = pl180_transfer_command(pdat, cmd);
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if (ret < 0) return ret;
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write32(pdat->virt + PL180_DATA_CTRL, dctrl);
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ret = write_bytes(pdat, (rt_uint32_t *)dat->buf, dat->blkcnt, dat->blksz);
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}
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return ret;
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}
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static rt_err_t sdhci_pl180_detect(struct sdhci_t * sdhci)
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{
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return RT_EOK;
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}
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static rt_err_t sdhci_pl180_setwidth(struct sdhci_t * sdhci, rt_uint32_t width)
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{
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return RT_EOK;
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}
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static rt_err_t sdhci_pl180_setclock(struct sdhci_t * sdhci, rt_uint32_t clock)
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{
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rt_uint32_t temp = 0;
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struct sdhci_pl180_pdata_t * pdat = (struct sdhci_pl180_pdata_t *)sdhci->priv;
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if(clock)
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{
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temp = read32(pdat->virt + PL180_CLOCK) | (0x1<<8);
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temp = temp; // skip warning
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write32(pdat->virt + PL180_CLOCK, 0x100);
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}
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else
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{
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//write32(pdat->virt + PL180_CLOCK, read32(pdat->virt + PL180_CLOCK) & (~(0x1<<8)));
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}
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return RT_EOK;
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}
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static rt_err_t sdhci_pl180_transfer(struct sdhci_t * sdhci, struct sdhci_cmd_t * cmd, struct sdhci_data_t * dat)
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{
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struct sdhci_pl180_pdata_t * pdat = (struct sdhci_pl180_pdata_t *)sdhci->priv;
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if(!dat)
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return pl180_transfer_command(pdat, cmd);
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return pl180_transfer_data(pdat, cmd, dat);
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}
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static void mmc_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
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{
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struct sdhci_t *sdhci = (struct sdhci_t *)host->private_data;
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struct sdhci_cmd_t cmd;
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struct sdhci_cmd_t stop;
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struct sdhci_data_t dat;
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rt_memset(&cmd, 0, sizeof(struct sdhci_cmd_t));
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rt_memset(&stop, 0, sizeof(struct sdhci_cmd_t));
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rt_memset(&dat, 0, sizeof(struct sdhci_data_t));
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cmd.cmdidx = req->cmd->cmd_code;
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cmd.cmdarg = req->cmd->arg;
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if (req->cmd->flags & RESP_MASK)
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{
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cmd.resptype = PL180_RSP_PRESENT;
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if (resp_type(req->cmd) == RESP_R2)
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cmd.resptype |= PL180_RSP_136BIT;
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}
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else
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cmd.resptype = 0;
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if(req->data)
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{
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dat.buf = (rt_uint8_t *)req->data->buf;
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dat.flag = req->data->flags;
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dat.blksz = req->data->blksize;
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dat.blkcnt = req->data->blks;
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req->cmd->err = sdhci_pl180_transfer(sdhci, &cmd, &dat);
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}
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else
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{
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req->cmd->err = sdhci_pl180_transfer(sdhci, &cmd, RT_NULL);
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}
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LOG_D("cmdarg:%d", cmd.cmdarg);
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LOG_D("cmdidx:%d", cmd.cmdidx);
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LOG_D("[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x", cmd.response[0], cmd.response[1], cmd.response[2], cmd.response[3]);
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req->cmd->resp[3] = cmd.response[3];
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req->cmd->resp[2] = cmd.response[2];
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req->cmd->resp[1] = cmd.response[1];
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req->cmd->resp[0] = cmd.response[0];
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if (req->stop)
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{
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stop.cmdidx = req->stop->cmd_code;
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stop.cmdarg = req->stop->arg;
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if (req->stop->flags & RESP_MASK)
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{
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stop.resptype = PL180_RSP_PRESENT;
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if (resp_type(req->stop) == RESP_R2)
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stop.resptype |= PL180_RSP_136BIT;
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}
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else
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stop.resptype = 0;
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req->stop->err = sdhci_pl180_transfer(sdhci, &stop, RT_NULL);
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}
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mmcsd_req_complete(host);
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}
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static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
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{
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struct sdhci_t * sdhci = (struct sdhci_t *)host->private_data;
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sdhci_pl180_setclock(sdhci, io_cfg->clock);
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sdhci_pl180_setwidth(sdhci, io_cfg->bus_width);
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LOG_D("clock:%d bus_width:%d", io_cfg->clock, io_cfg->bus_width);
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}
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static const struct rt_mmcsd_host_ops ops =
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{
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mmc_request_send,
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mmc_set_iocfg,
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RT_NULL,
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RT_NULL,
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};
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int pl180_init(void)
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{
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rt_uint32_t virt;
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rt_uint32_t id;
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struct rt_mmcsd_host * host = RT_NULL;
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struct sdhci_pl180_pdata_t * pdat = RT_NULL;
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struct sdhci_t * sdhci = RT_NULL;
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host = mmcsd_alloc_host();
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if (!host)
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{
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LOG_E("alloc host failed");
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goto err;
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}
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sdhci = rt_malloc(sizeof(struct sdhci_t));
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if (!sdhci)
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{
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LOG_E("alloc sdhci failed");
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goto err;
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}
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rt_memset(sdhci, 0, sizeof(struct sdhci_t));
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virt = MMC_BASE_ADDR;
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id = (((read32((virt + 0xfec)) & 0xff) << 24) |
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((read32((virt + 0xfe8)) & 0xff) << 16) |
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((read32((virt + 0xfe4)) & 0xff) << 8) |
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((read32((virt + 0xfe0)) & 0xff) << 0));
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LOG_D("id=0x%08x", id);
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if(((id >> 12) & 0xff) != 0x41 || (id & 0xfff) != 0x181)
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{
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LOG_E("check id failed");
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goto err;
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}
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pdat = (struct sdhci_pl180_pdata_t *)rt_malloc(sizeof(struct sdhci_pl180_pdata_t));
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RT_ASSERT(pdat != RT_NULL);
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pdat->virt = (uint32_t)virt;
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sdhci->name = "sd0";
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sdhci->voltages = VDD_33_34;
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sdhci->width = MMCSD_BUSWIDTH_4;
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sdhci->clock = 26 * 1000 * 1000;
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sdhci->removeable = RT_TRUE;
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sdhci->detect = sdhci_pl180_detect;
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sdhci->setwidth = sdhci_pl180_setwidth;
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sdhci->setclock = sdhci_pl180_setclock;
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sdhci->transfer = sdhci_pl180_transfer;
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sdhci->priv = pdat;
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write32(pdat->virt + PL180_POWER, 0xbf);
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host->ops = &ops;
|
|
host->freq_min = 400000;
|
|
host->freq_max = 50000000;
|
|
host->valid_ocr = VDD_32_33 | VDD_33_34;
|
|
host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ | MMCSD_BUSWIDTH_4;
|
|
host->max_seg_size = 2048;
|
|
host->max_dma_segs = 10;
|
|
host->max_blk_size = 512;
|
|
host->max_blk_count = 4096;
|
|
|
|
host->private_data = sdhci;
|
|
|
|
mmcsd_change(host);
|
|
|
|
return RT_EOK;
|
|
|
|
err:
|
|
if(host) rt_free(host);
|
|
if(sdhci) rt_free(sdhci);
|
|
|
|
return -RT_EIO;
|
|
}
|
|
INIT_DEVICE_EXPORT(pl180_init);
|
|
|
|
#endif
|