204 lines
6.4 KiB
C
204 lines
6.4 KiB
C
/*
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* Copyright (c) 2011-2012, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*!
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* @file epit.c
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* @brief EPIT driver source file.
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*
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* @ingroup diag_timer
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*/
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#include "epit.h"
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#include "imx_timer.h"
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#include "interrupt.h"
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#include "ccm_pll.h"
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#include "registers/regsepit.h"
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////////////////////////////////////////////////////////////////////////////////
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// Code
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////////////////////////////////////////////////////////////////////////////////
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void epit_reload_counter(uint32_t instance, uint32_t load_val)
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{
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// set the load register especially if RLD=reload_mode=SET_AND_FORGET=1
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HW_EPIT_LR_WR(instance, load_val);
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}
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uint32_t epit_get_counter_value(uint32_t instance)
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{
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return HW_EPIT_CNR_RD(instance);
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}
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void epit_set_compare_event(uint32_t instance, uint32_t compare_val)
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{
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HW_EPIT_CMPR_WR(instance, compare_val);
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}
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uint32_t epit_get_compare_event(uint32_t instance)
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{
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uint32_t status_register;
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// get the status
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status_register = HW_EPIT_SR_RD(instance);
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// clear it if found set
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if (status_register & BM_EPIT_SR_OCIF)
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{
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HW_EPIT_SR_SET(instance, BM_EPIT_SR_OCIF);
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}
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// return the read value before the bit was cleared
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return status_register & BM_EPIT_SR_OCIF;
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}
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void epit_counter_disable(uint32_t instance)
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{
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/* temporary workaround for the discovered issue when disabling the
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* counter during end of count/reload/set compare flag ??.
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* Set to the max value so that it ensures that the counter couldn't
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* reach 0 when it is disabled.
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*/
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HW_EPIT_LR_WR(instance, 0xFFFFFFFF);
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// disable the counter
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HW_EPIT_CR_CLR(instance, BM_EPIT_CR_EN);
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// ensure to leave the counter in a proper state
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// by disabling the output compare interrupt
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HW_EPIT_CR_CLR(instance, BM_EPIT_CR_OCIEN);
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// and clearing possible remaining compare event
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HW_EPIT_SR_SET(instance, BM_EPIT_SR_OCIF);
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}
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void epit_counter_enable(uint32_t instance, uint32_t load_val, uint32_t irq_mode)
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{
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// set the load register especially if RLD=reload_mode=SET_AND_FORGET=1
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// and if the value is different from 0 which is the lowest counter value
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if (load_val != 0)
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{
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HW_EPIT_LR_WR(instance, load_val);
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}
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// ensure to start the counter in a proper state
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// by clearing possible remaining compare event
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HW_EPIT_SR_SET(instance, BM_EPIT_SR_OCIF);
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// set the mode when the output compare event occur: IRQ or polling
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if (irq_mode == IRQ_MODE)
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{
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HW_EPIT_CR_SET(instance, BM_EPIT_CR_OCIEN);
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}
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else
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{
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// polling
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HW_EPIT_CR_CLR(instance, BM_EPIT_CR_OCIEN);
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}
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// finally, enable the counter
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HW_EPIT_CR_SET(instance, BM_EPIT_CR_EN);
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}
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void epit_setup_interrupt(uint32_t instance, void (*irq_subroutine)(void), bool enableIt)
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{
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uint32_t irq_id = EPIT_IRQS(instance);
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if (enableIt)
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{
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// register the IRQ sub-routine
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register_interrupt_routine(irq_id, irq_subroutine);
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// enable the IRQ
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enable_interrupt(irq_id, CPU_0, 0);
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}
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else
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{
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// disable the IRQ
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disable_interrupt(irq_id, CPU_0);
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}
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}
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void epit_init(uint32_t instance, uint32_t clock_src, uint32_t prescaler,
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uint32_t reload_mode, uint32_t load_val, uint32_t low_power_mode)
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{
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uint32_t control_reg_tmp = 0;
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uint32_t base = REGS_EPIT_BASE(instance);
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// enable the source clocks to the EPIT port
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clock_gating_config(base, CLOCK_ON);
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// start with a known state by disabling and reseting the module
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HW_EPIT_CR_WR(instance, BM_EPIT_CR_SWR);
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// wait for the reset to complete
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while ((HW_EPIT_CR(instance).B.SWR) != 0) ;
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// set the reference source clock for the counter
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control_reg_tmp |= BF_EPIT_CR_CLKSRC(clock_src);
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// set the counter clock prescaler value - 0 to 4095
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control_reg_tmp |= BF_EPIT_CR_PRESCALAR(prescaler-1);
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// set the reload mode
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if (reload_mode == SET_AND_FORGET)
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{
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control_reg_tmp |= BM_EPIT_CR_RLD;
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}
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// set behavior for low power mode
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if (low_power_mode & WAIT_MODE_EN)
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{
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control_reg_tmp |= BM_EPIT_CR_WAITEN;
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}
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if (low_power_mode & STOP_MODE_EN)
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{
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control_reg_tmp |= BM_EPIT_CR_STOPEN;
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}
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// make the counter start from a known value when enabled, this is loaded from
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// EPITLR register if RLD=reload_mode=1 or 0xFFFFFFFF if RLD=reload_mode=0
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control_reg_tmp |= BM_EPIT_CR_IOVW | BM_EPIT_CR_ENMOD;
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// finally write the control register
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HW_EPIT_CR_WR(instance, control_reg_tmp);
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// initialize the load register especially if RLD=reload_mode=SET_AND_FORGET=1
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// and if the value is different from 0 which is the lowest counter value
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if (load_val != 0)
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{
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HW_EPIT_LR_WR(instance, load_val);
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}
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}
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////////////////////////////////////////////////////////////////////////////////
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// EOF
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////////////////////////////////////////////////////////////////////////////////
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