124 lines
4.4 KiB
C
124 lines
4.4 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fadc_hw.h
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-18 08:28:45
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* Description: This file is for adc register definition.
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 wangxiaodong 2022/4/15 init commit
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*/
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#ifndef FADC_HW_H
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#define FADC_HW_H
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#include "fkernel.h"
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#include "ftypes.h"
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#include "fio.h"
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#include "fdebug.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Generic ADC register definitions */
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/* FADC register */
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#define FADC_CTRL_REG_OFFSET 0x00
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#define FADC_INTER_REG_OFFSET 0x04
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#define FADC_STATE_REG_OFFSET 0x08
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#define FADC_ERRCLR_REG_OFFSET 0x0c
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#define FADC_LEVEL_REG_OFFSET(x) (0x10+(x)*4)
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#define FADC_INTRMASK_REG_OFFSET 0x30
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#define FADC_INTR_REG_OFFSET 0x34
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#define FADC_COV_RESULT_REG_OFFSET(x) (0x38+(x)*4)
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#define FADC_FINISH_CNT_REG_OFFSET(x) (0x58+(x)*4)
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#define FADC_HIS_LIMIT_REG_OFFSET(x) (0x78+(x)*4)
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#define FADC_CTRL_REG_PD_EN BIT(31)
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#define FADC_CTRL_REG_FIX_CHANNEL_NUM_MASK GENMASK(18, 16)
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#define FADC_CTRL_REG_FIX_CHANNEL_NUM(x) ((x)<<16)
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#define FADC_CTRL_REG_CLK_DIV(x) ((x)<<12)
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#define FADC_CTRL_REG_CLK_DIV_MASK GENMASK(15, 12)
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#define FADC_CTRL_REG_CHANNEL_EN(x) BIT((x)+4)
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#define FADC_CTRL_REG_FIX_CHANNEL BIT(3)
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#define FADC_CTRL_REG_SINGLE_CONVERT_EN BIT(2)
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#define FADC_CTRL_REG_SINGLE_CONVERT BIT(1)
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#define FADC_CTRL_REG_SOC_EN BIT(0)
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#define FADC_STATE_REG_B_STA(x) ((x)<<8)
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#define FADC_STATE_REG_EOC_STA BIT(7)
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#define FADC_STATE_REG_S_STA(x) ((x)<<4)
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#define FADC_STATE_REG_SOC_STA BIT(3)
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#define FADC_STATE_REG_ERR_STA BIT(2)
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#define FADC_STATE_REG_COV_FINISH_STA BIT(1)
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#define FADC_STATE_REG_CTL_BUSY_STA BIT(0)
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#define FADC_LEVEL_REG_HIGH_LEVEL(x) ((x)<<16)
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#define FADC_LEVEL_REG_LOW_LEVEL(x) ((x)<<0)
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#define FADC_INTRMASK_REG_ERR_MASK BIT(24)
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#define FADC_INTRMASK_REG_ULIMIT_MASK(x) BIT((x)*2+9)
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#define FADC_INTRMASK_REG_DLIMIT_MASK(x) BIT((x)*2+8)
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#define FADC_INTRMASK_REG_COVFIN_MASK(x) BIT((x))
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#define FADC_INTR_REG_ERR BIT(24)
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#define FADC_INTR_REG_ULIMIT(x) BIT((x)*2+9)
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#define FADC_INTR_REG_DLIMIT(x) BIT((x)*2+8)
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#define FADC_INTR_REG_COVFIN(x) BIT((x))
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#define FADC_INTR_REG_COVFIN_MASK GENMASK(7, 0)
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#define FADC_INTR_REG_LIMIT_MASK GENMASK(23, 8)
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/* convert result range */
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#define FADC_COV_RESULT_REG_MASK GENMASK(9, 0)
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#define FADC_HIS_LIMIT_REG_UMASK GENMASK(25, 16)
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#define FADC_HIS_LIMIT_REG_DMASK GENMASK(9, 0)
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/***************** Macros (Inline Functions) Definitions *********************/
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/**
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* @name: FADC_READ_REG32
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* @msg: 读取FADC寄存器
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* @param {u32} addr 定时器的基地址
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* @param {u32} reg_offset 定时器的寄存器的偏移
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* @return {u32} 寄存器参数
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*/
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#define FADC_READ_REG32(addr, reg_offset) FtIn32(addr + (u32)(reg_offset))
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/**
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* @name: FADC_WRITE_REG32
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* @msg: 写入FADC寄存器
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* @param {u32} addr 定时器的基地址
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* @param {u32} reg_offset 定时器的寄存器的偏移
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* @param {u32} reg_value 写入寄存器参数
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* @return {void}
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*/
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#define FADC_WRITE_REG32(addr, reg_offset, reg_value) FtOut32((addr) + (u32)(reg_offset), (u32)(reg_value))
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#define FADC_SETBIT(base_addr, reg_offset, data) FtSetBit32((base_addr) + (u32)(reg_offset), (u32)(data))
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#define FADC_CLEARBIT(base_addr, reg_offset, data) FtClearBit32((base_addr) + (u32)(reg_offset), (u32)(data))
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/* debug register value for adc channel */
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void FAdcDump(uintptr base_addr, u8 channel);
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#ifdef __cplusplus
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}
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#endif
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#endif |