493 lines
12 KiB
C
493 lines
12 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-01-30 lizhirui first version
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* 2022-12-13 WangXiaoyao Port to new mm
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*/
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#include <rtthread.h>
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#include <stddef.h>
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#include <stdint.h>
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#define DBG_TAG "hw.mmu"
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#define DBG_LVL DBG_INFO
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#include <rtdbg.h>
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#include <board.h>
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#include <cache.h>
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#include <mm_aspace.h>
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#include <mm_page.h>
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#include <mmu.h>
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#include <riscv_mmu.h>
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#include <tlb.h>
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#ifdef RT_USING_SMART
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#include <board.h>
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#include <ioremap.h>
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#include <lwp_user_mm.h>
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#endif
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#ifndef RT_USING_SMART
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#define USER_VADDR_START 0
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#endif
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static size_t _unmap_area(struct rt_aspace *aspace, void *v_addr, size_t size);
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static void *current_mmu_table = RT_NULL;
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volatile __attribute__((aligned(4 * 1024)))
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rt_ubase_t MMUTable[__SIZE(VPN2_BIT)];
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void rt_hw_aspace_switch(rt_aspace_t aspace)
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{
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uintptr_t page_table = (uintptr_t)rt_kmem_v2p(aspace->page_table);
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current_mmu_table = aspace->page_table;
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write_csr(satp, (((size_t)SATP_MODE) << SATP_MODE_OFFSET) |
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((rt_ubase_t)page_table >> PAGE_OFFSET_BIT));
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rt_hw_tlb_invalidate_all_local();
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}
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void *rt_hw_mmu_tbl_get()
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{
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return current_mmu_table;
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}
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static int _map_one_page(struct rt_aspace *aspace, void *va, void *pa,
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size_t attr)
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{
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rt_size_t l1_off, l2_off, l3_off;
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rt_size_t *mmu_l1, *mmu_l2, *mmu_l3;
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l1_off = GET_L1((size_t)va);
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l2_off = GET_L2((size_t)va);
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l3_off = GET_L3((size_t)va);
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mmu_l1 = ((rt_size_t *)aspace->page_table) + l1_off;
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if (PTE_USED(*mmu_l1))
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{
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mmu_l2 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l1), PV_OFFSET);
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}
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else
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{
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mmu_l2 = (rt_size_t *)rt_pages_alloc(0);
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if (mmu_l2)
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{
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rt_memset(mmu_l2, 0, PAGE_SIZE);
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rt_hw_cpu_dcache_clean(mmu_l2, PAGE_SIZE);
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*mmu_l1 = COMBINEPTE((rt_size_t)VPN_TO_PPN(mmu_l2, PV_OFFSET),
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PAGE_DEFAULT_ATTR_NEXT);
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rt_hw_cpu_dcache_clean(mmu_l1, sizeof(*mmu_l1));
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}
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else
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{
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return -1;
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}
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}
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if (PTE_USED(*(mmu_l2 + l2_off)))
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{
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RT_ASSERT(!PAGE_IS_LEAF(*(mmu_l2 + l2_off)));
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mmu_l3 =
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(rt_size_t *)PPN_TO_VPN(GET_PADDR(*(mmu_l2 + l2_off)), PV_OFFSET);
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}
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else
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{
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mmu_l3 = (rt_size_t *)rt_pages_alloc(0);
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if (mmu_l3)
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{
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rt_memset(mmu_l3, 0, PAGE_SIZE);
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rt_hw_cpu_dcache_clean(mmu_l3, PAGE_SIZE);
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*(mmu_l2 + l2_off) =
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COMBINEPTE((rt_size_t)VPN_TO_PPN(mmu_l3, PV_OFFSET),
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PAGE_DEFAULT_ATTR_NEXT);
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rt_hw_cpu_dcache_clean(mmu_l2, sizeof(*mmu_l2));
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// declares a reference to parent page table
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rt_page_ref_inc((void *)mmu_l2, 0);
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}
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else
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{
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return -1;
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}
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}
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RT_ASSERT(!PTE_USED(*(mmu_l3 + l3_off)));
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// declares a reference to parent page table
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rt_page_ref_inc((void *)mmu_l3, 0);
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*(mmu_l3 + l3_off) = COMBINEPTE((rt_size_t)pa, attr);
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rt_hw_cpu_dcache_clean(mmu_l3 + l3_off, sizeof(*(mmu_l3 + l3_off)));
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return 0;
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}
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/** rt_hw_mmu_map will never override existed page table entry */
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void *rt_hw_mmu_map(struct rt_aspace *aspace, void *v_addr, void *p_addr,
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size_t size, size_t attr)
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{
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int ret = -1;
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void *unmap_va = v_addr;
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size_t npages = size >> ARCH_PAGE_SHIFT;
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// TODO trying with HUGEPAGE here
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while (npages--)
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{
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MM_PGTBL_LOCK(aspace);
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ret = _map_one_page(aspace, v_addr, p_addr, attr);
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MM_PGTBL_UNLOCK(aspace);
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if (ret != 0)
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{
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/* error, undo map */
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while (unmap_va != v_addr)
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{
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MM_PGTBL_LOCK(aspace);
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_unmap_area(aspace, unmap_va, ARCH_PAGE_SIZE);
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MM_PGTBL_UNLOCK(aspace);
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unmap_va += ARCH_PAGE_SIZE;
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}
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break;
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}
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v_addr += ARCH_PAGE_SIZE;
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p_addr += ARCH_PAGE_SIZE;
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}
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if (ret == 0)
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{
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return unmap_va;
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}
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return NULL;
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}
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static void _unmap_pte(rt_size_t *pentry, rt_size_t *lvl_entry[], int level)
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{
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int loop_flag = 1;
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while (loop_flag)
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{
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loop_flag = 0;
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*pentry = 0;
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rt_hw_cpu_dcache_clean(pentry, sizeof(*pentry));
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// we don't handle level 0, which is maintained by caller
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if (level > 0)
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{
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void *page = (void *)((rt_ubase_t)pentry & ~ARCH_PAGE_MASK);
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// decrease reference from child page to parent
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rt_pages_free(page, 0);
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int free = rt_page_ref_get(page, 0);
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if (free == 1)
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{
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rt_pages_free(page, 0);
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pentry = lvl_entry[--level];
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loop_flag = 1;
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}
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}
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}
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}
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static size_t _unmap_area(struct rt_aspace *aspace, void *v_addr, size_t size)
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{
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rt_size_t loop_va = __UMASKVALUE((rt_size_t)v_addr, PAGE_OFFSET_MASK);
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size_t unmapped = 0;
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int i = 0;
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rt_size_t lvl_off[3];
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rt_size_t *lvl_entry[3];
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lvl_off[0] = (rt_size_t)GET_L1(loop_va);
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lvl_off[1] = (rt_size_t)GET_L2(loop_va);
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lvl_off[2] = (rt_size_t)GET_L3(loop_va);
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unmapped = 1 << (ARCH_PAGE_SHIFT + ARCH_INDEX_WIDTH * 2ul);
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rt_size_t *pentry;
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lvl_entry[i] = ((rt_size_t *)aspace->page_table + lvl_off[i]);
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pentry = lvl_entry[i];
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// find leaf page table entry
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while (PTE_USED(*pentry) && !PAGE_IS_LEAF(*pentry))
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{
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i += 1;
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lvl_entry[i] = ((rt_size_t *)PPN_TO_VPN(GET_PADDR(*pentry), PV_OFFSET) +
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lvl_off[i]);
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pentry = lvl_entry[i];
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unmapped >>= ARCH_INDEX_WIDTH;
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}
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// clear PTE & setup its
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if (PTE_USED(*pentry))
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{
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_unmap_pte(pentry, lvl_entry, i);
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}
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return unmapped;
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}
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/** unmap is different from map that it can handle multiple pages */
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void rt_hw_mmu_unmap(struct rt_aspace *aspace, void *v_addr, size_t size)
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{
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// caller guarantee that v_addr & size are page aligned
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if (!aspace->page_table)
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{
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return;
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}
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size_t unmapped = 0;
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while (size > 0)
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{
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MM_PGTBL_LOCK(aspace);
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unmapped = _unmap_area(aspace, v_addr, size);
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MM_PGTBL_UNLOCK(aspace);
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// when unmapped == 0, region not exist in pgtbl
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if (!unmapped || unmapped > size)
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break;
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size -= unmapped;
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v_addr += unmapped;
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}
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}
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#ifdef RT_USING_SMART
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static inline void _init_region(void *vaddr, size_t size)
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{
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rt_ioremap_start = vaddr;
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rt_ioremap_size = size;
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rt_mpr_start = rt_ioremap_start - rt_mpr_size;
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LOG_D("rt_ioremap_start: %p, rt_mpr_start: %p", rt_ioremap_start, rt_mpr_start);
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}
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#else
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static inline void _init_region(void *vaddr, size_t size)
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{
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rt_mpr_start = vaddr - rt_mpr_size;
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}
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#endif
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int rt_hw_mmu_map_init(rt_aspace_t aspace, void *v_address, rt_size_t size,
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rt_size_t *vtable, rt_size_t pv_off)
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{
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size_t l1_off, va_s, va_e;
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rt_base_t level;
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if ((!aspace) || (!vtable))
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{
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return -1;
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}
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va_s = (rt_size_t)v_address;
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va_e = ((rt_size_t)v_address) + size - 1;
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if (va_e < va_s)
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{
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return -1;
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}
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// convert address to PPN2 index
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va_s = GET_L1(va_s);
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va_e = GET_L1(va_e);
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if (va_s == 0)
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{
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return -1;
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}
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// vtable initialization check
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for (l1_off = va_s; l1_off <= va_e; l1_off++)
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{
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size_t v = vtable[l1_off];
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if (v)
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{
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return -1;
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}
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}
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rt_aspace_init(&rt_kernel_space, (void *)0x1000, USER_VADDR_START - 0x1000,
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vtable);
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_init_region(v_address, size);
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return 0;
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}
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const static int max_level =
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(ARCH_VADDR_WIDTH - ARCH_PAGE_SHIFT) / ARCH_INDEX_WIDTH;
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static inline uintptr_t _get_level_size(int level)
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{
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return 1ul << (ARCH_PAGE_SHIFT + (max_level - level) * ARCH_INDEX_WIDTH);
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}
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static rt_size_t *_query(struct rt_aspace *aspace, void *vaddr, int *level)
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{
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rt_size_t l1_off, l2_off, l3_off;
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rt_size_t *mmu_l1, *mmu_l2, *mmu_l3;
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rt_size_t pa;
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l1_off = GET_L1((rt_size_t)vaddr);
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l2_off = GET_L2((rt_size_t)vaddr);
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l3_off = GET_L3((rt_size_t)vaddr);
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if (!aspace)
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{
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LOG_W("%s: no aspace", __func__);
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return RT_NULL;
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}
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mmu_l1 = ((rt_size_t *)aspace->page_table) + l1_off;
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if (PTE_USED(*mmu_l1))
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{
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if (*mmu_l1 & PTE_XWR_MASK)
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{
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*level = 1;
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return mmu_l1;
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}
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mmu_l2 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*mmu_l1), PV_OFFSET);
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if (PTE_USED(*(mmu_l2 + l2_off)))
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{
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if (*(mmu_l2 + l2_off) & PTE_XWR_MASK)
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{
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*level = 2;
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return mmu_l2 + l2_off;
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}
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mmu_l3 = (rt_size_t *)PPN_TO_VPN(GET_PADDR(*(mmu_l2 + l2_off)),
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PV_OFFSET);
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if (PTE_USED(*(mmu_l3 + l3_off)))
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{
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*level = 3;
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return mmu_l3 + l3_off;
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}
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}
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}
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return RT_NULL;
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}
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void *rt_hw_mmu_v2p(struct rt_aspace *aspace, void *vaddr)
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{
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int level;
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uintptr_t *pte = _query(aspace, vaddr, &level);
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uintptr_t paddr;
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if (pte)
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{
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paddr = GET_PADDR(*pte);
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paddr |= ((intptr_t)vaddr & (_get_level_size(level) - 1));
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}
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else
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{
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paddr = (uintptr_t)ARCH_MAP_FAILED;
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}
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return (void *)paddr;
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}
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static int _noncache(uintptr_t *pte)
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{
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return 0;
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}
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static int _cache(uintptr_t *pte)
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{
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return 0;
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}
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static int (*control_handler[MMU_CNTL_DUMMY_END])(uintptr_t *pte) = {
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[MMU_CNTL_CACHE] = _cache,
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[MMU_CNTL_NONCACHE] = _noncache,
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};
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int rt_hw_mmu_control(struct rt_aspace *aspace, void *vaddr, size_t size,
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enum rt_mmu_cntl cmd)
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{
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int level;
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int err = -RT_EINVAL;
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void *vend = vaddr + size;
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int (*handler)(uintptr_t * pte);
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if (cmd >= 0 && cmd < MMU_CNTL_DUMMY_END)
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{
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handler = control_handler[cmd];
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while (vaddr < vend)
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{
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uintptr_t *pte = _query(aspace, vaddr, &level);
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void *range_end = vaddr + _get_level_size(level);
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RT_ASSERT(range_end <= vend);
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if (pte)
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{
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err = handler(pte);
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RT_ASSERT(err == RT_EOK);
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}
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vaddr = range_end;
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}
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}
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else
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{
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err = -RT_ENOSYS;
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}
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return err;
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}
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/**
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* @brief setup Page Table for kernel space. It's a fixed map
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* and all mappings cannot be changed after initialization.
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*
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* Memory region in struct mem_desc must be page aligned,
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* otherwise is a failure and no report will be
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* returned.
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*
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* @param aspace
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* @param mdesc
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* @param desc_nr
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*/
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void rt_hw_mmu_setup(rt_aspace_t aspace, struct mem_desc *mdesc, int desc_nr)
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{
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void *err;
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for (size_t i = 0; i < desc_nr; i++)
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{
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size_t attr;
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switch (mdesc->attr)
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{
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case NORMAL_MEM:
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attr = MMU_MAP_K_RWCB;
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break;
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case NORMAL_NOCACHE_MEM:
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attr = MMU_MAP_K_RWCB;
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break;
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case DEVICE_MEM:
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attr = MMU_MAP_K_DEVICE;
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break;
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default:
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attr = MMU_MAP_K_DEVICE;
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}
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struct rt_mm_va_hint hint = {.flags = MMF_MAP_FIXED,
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.limit_start = aspace->start,
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.limit_range_size = aspace->size,
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.map_size = mdesc->vaddr_end -
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mdesc->vaddr_start + 1,
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.prefer = (void *)mdesc->vaddr_start};
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if (mdesc->paddr_start == (rt_size_t)ARCH_MAP_FAILED)
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mdesc->paddr_start = mdesc->vaddr_start + PV_OFFSET;
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rt_aspace_map_phy_static(aspace, &mdesc->varea, &hint, attr,
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mdesc->paddr_start >> MM_PAGE_SHIFT, &err);
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mdesc++;
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}
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rt_hw_aspace_switch(&rt_kernel_space);
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rt_page_cleanup();
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}
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