119 lines
5.3 KiB
Plaintext
119 lines
5.3 KiB
Plaintext
/*
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** ###################################################################
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** Processors: MIMXRT1021CAF4A
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** MIMXRT1021CAG4A
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** MIMXRT1021DAF5A
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** MIMXRT1021DAG5A
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**
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** Compiler: IAR ANSI C/C++ Compiler for ARM
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** Reference manual: IMXRT1020RM Rev. C, 02/2018
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** Version: rev. 0.1, 2017-06-06
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** Build: b180316
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**
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** Abstract:
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** Linker file for the IAR ANSI C/C++ Compiler for ARM
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**
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** The Clear BSD License
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2018 NXP
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** All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without
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** modification, are permitted (subject to the limitations in the
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** disclaimer below) provided that the following conditions are met:
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**
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** * Redistributions of source code must retain the above copyright
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** notice, this list of conditions and the following disclaimer.
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**
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** * Redistributions in binary form must reproduce the above copyright
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** notice, this list of conditions and the following disclaimer in the
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** documentation and/or other materials provided with the distribution.
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**
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** * Neither the name of the copyright holder nor the names of its
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** contributors may be used to endorse or promote products derived from
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** this software without specific prior written permission.
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**
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** NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
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** GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
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** HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
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** WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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** MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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** LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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** CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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** SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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** BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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** WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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** OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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** IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** ###################################################################
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*/
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define symbol m_interrupts_start = 0x00000000;
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define symbol m_interrupts_end = 0x000003FF;
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define symbol m_text_start = 0x00000400;
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define symbol m_text_end = 0x0000FFFF;
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define symbol m_data_start = 0x20000000;
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define symbol m_data_end = 0x2000FFFF;
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define symbol m_data2_start = 0x20200000;
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define symbol m_data2_end = 0x2021FFFF;
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define symbol m_data3_start = 0x80000000;
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define symbol m_data3_end = 0x81DFFFFF;
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define symbol m_ncache_start = 0x81E00000;
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define symbol m_ncache_end = 0x81FFFFFF;
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/* Sizes */
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if (isdefinedsymbol(__stack_size__)) {
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define symbol __size_cstack__ = __stack_size__;
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} else {
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define symbol __size_cstack__ = 0x0400;
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}
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if (isdefinedsymbol(__heap_size__)) {
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define symbol __size_heap__ = __heap_size__;
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} else {
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define symbol __size_heap__ = 0x0400;
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}
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define exported symbol __VECTOR_TABLE = m_interrupts_start;
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define exported symbol __VECTOR_RAM = m_interrupts_start;
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define exported symbol __RAM_VECTOR_TABLE_SIZE = 0x0;
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define memory mem with size = 4G;
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define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
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| mem:[from m_text_start to m_text_end];
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define region DATA_region = mem:[from m_data_start to m_data_end];
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define region DATA2_region = mem:[from m_data2_start to m_data2_end];
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define region DATA3_region = mem:[from m_data3_start to m_data3_end-__size_cstack__];
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define region CSTACK_region = mem:[from m_data3_end-__size_cstack__+1 to m_data3_end];
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define region NCACHE_region = mem:[from m_ncache_start to m_ncache_end];
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define block CSTACK with alignment = 8, size = __size_cstack__ { };
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define block HEAP with alignment = 8, size = __size_heap__ { };
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define block RW { first readwrite, section m_usb_dma_init_data };
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define block ZI with alignment = 32 { first zi, section m_usb_dma_noninit_data };
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define block NCACHE_VAR with size = 0x200000 , alignment = 0x100000 { section NonCacheable , section NonCacheable.init };
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initialize by copy { readwrite, section .textrw };
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do not initialize { section .noinit };
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place at address mem: m_interrupts_start { readonly section .intvec };
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place in TEXT_region { readonly };
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place in DATA3_region { block RW };
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place in DATA3_region { block ZI };
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place in DATA3_region { last block HEAP };
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place in CSTACK_region { block CSTACK };
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place in NCACHE_region { block NCACHE_VAR };
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