478 lines
15 KiB
C
478 lines
15 KiB
C
/*
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* The Clear BSD License
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* Copyright 2017 NXP
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_qtmr.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.qtmr"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Gets the instance from the base address to be used to gate or ungate the module clock
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*
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* @param base Quad Timer peripheral base address
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*
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* @return The Quad Timer instance
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*/
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static uint32_t QTMR_GetInstance(TMR_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Pointers to Quad Timer bases for each instance. */
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static TMR_Type *const s_qtmrBases[] = TMR_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to Quad Timer clocks for each instance. */
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static const clock_ip_name_t s_qtmrClocks[] = TMR_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t QTMR_GetInstance(TMR_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_qtmrBases); instance++)
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{
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if (s_qtmrBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_qtmrBases));
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return instance;
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}
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void QTMR_Init(TMR_Type *base, qtmr_channel_selection_t channel, const qtmr_config_t *config)
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{
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assert(config);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the module clock */
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CLOCK_EnableClock(s_qtmrClocks[QTMR_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Setup the counter sources */
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base->CHANNEL[channel].CTRL = (TMR_CTRL_PCS(config->primarySource) | TMR_CTRL_SCS(config->secondarySource));
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/* Setup the master mode operation */
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base->CHANNEL[channel].SCTRL = (TMR_SCTRL_EEOF(config->enableExternalForce) | TMR_SCTRL_MSTR(config->enableMasterMode));
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/* Setup debug mode */
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base->CHANNEL[channel].CSCTRL = TMR_CSCTRL_DBG_EN(config->debugMode);
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base->CHANNEL[channel].FILT &= ~( TMR_FILT_FILT_CNT_MASK | TMR_FILT_FILT_PER_MASK);
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/* Setup input filter */
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base->CHANNEL[channel].FILT = (TMR_FILT_FILT_CNT(config->faultFilterCount) | TMR_FILT_FILT_PER(config->faultFilterPeriod));
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}
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void QTMR_Deinit(TMR_Type *base, qtmr_channel_selection_t channel)
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{
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/* Stop the counter */
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base->CHANNEL[channel].CTRL &= ~TMR_CTRL_CM_MASK;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the module clock */
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CLOCK_DisableClock(s_qtmrClocks[QTMR_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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void QTMR_GetDefaultConfig(qtmr_config_t *config)
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{
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assert(config);
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/* Halt counter during debug mode */
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config->debugMode = kQTMR_RunNormalInDebug;
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/* Another counter cannot force state of OFLAG signal */
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config->enableExternalForce = false;
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/* Compare function's output from this counter is not broadcast to other counters */
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config->enableMasterMode = false;
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/* Fault filter count is set to 0 */
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config->faultFilterCount = 0;
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/* Fault filter period is set to 0 which disables the fault filter */
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config->faultFilterPeriod = 0;
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/* Primary count source is IP bus clock divide by 2 */
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config->primarySource = kQTMR_ClockDivide_2;
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/* Secondary count source is counter 0 input pin */
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config->secondarySource = kQTMR_Counter0InputPin;
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}
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status_t QTMR_SetupPwm(
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TMR_Type *base, qtmr_channel_selection_t channel, uint32_t pwmFreqHz, uint8_t dutyCyclePercent, bool outputPolarity, uint32_t srcClock_Hz)
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{
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uint32_t periodCount, highCount, lowCount, reg;
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if (dutyCyclePercent > 100)
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{
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/* Invalid dutycycle */
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return kStatus_Fail;
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}
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/* Set OFLAG pin for output mode and force out a low on the pin */
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base->CHANNEL[channel].SCTRL |= (TMR_SCTRL_FORCE_MASK | TMR_SCTRL_OEN_MASK);
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/* Counter values to generate a PWM signal */
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periodCount = (srcClock_Hz / pwmFreqHz);
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highCount = (periodCount * dutyCyclePercent) / 100;
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lowCount = periodCount - highCount;
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/* Setup the compare registers for PWM output */
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base->CHANNEL[channel].COMP1 = lowCount;
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base->CHANNEL[channel].COMP2 = highCount;
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/* Setup the pre-load registers for PWM output */
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base->CHANNEL[channel].CMPLD1 = lowCount;
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base->CHANNEL[channel].CMPLD2 = highCount;
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reg = base->CHANNEL[channel].CSCTRL;
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/* Setup the compare load control for COMP1 and COMP2.
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* Load COMP1 when CSCTRL[TCF2] is asserted, load COMP2 when CSCTRL[TCF1] is asserted
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*/
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reg &= ~(TMR_CSCTRL_CL1_MASK | TMR_CSCTRL_CL2_MASK);
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reg |= (TMR_CSCTRL_CL1(kQTMR_LoadOnComp2) | TMR_CSCTRL_CL2(kQTMR_LoadOnComp1));
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base->CHANNEL[channel].CSCTRL = reg;
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if (outputPolarity)
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{
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/* Invert the polarity */
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base->CHANNEL[channel].SCTRL |= TMR_SCTRL_OPS_MASK;
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}
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else
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{
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/* True polarity, no inversion */
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base->CHANNEL[channel].SCTRL &= ~TMR_SCTRL_OPS_MASK;
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}
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reg = base->CHANNEL[channel].CTRL;
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reg &= ~(TMR_CTRL_OUTMODE_MASK);
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/* Count until compare value is reached and re-initialize the counter, toggle OFLAG output
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* using alternating compare register
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*/
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reg |= (TMR_CTRL_LENGTH_MASK | TMR_CTRL_OUTMODE(kQTMR_ToggleOnAltCompareReg));
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base->CHANNEL[channel].CTRL = reg;
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return kStatus_Success;
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}
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void QTMR_SetupInputCapture(TMR_Type *base,
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qtmr_channel_selection_t channel,
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qtmr_input_source_t capturePin,
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bool inputPolarity,
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bool reloadOnCapture,
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qtmr_input_capture_edge_t captureMode)
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{
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uint16_t reg;
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/* Clear the prior value for the input source for capture */
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reg = base->CHANNEL[channel].CTRL & (~TMR_CTRL_SCS_MASK);
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/* Set the new input source */
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reg |= TMR_CTRL_SCS(capturePin);
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base->CHANNEL[channel].CTRL = reg;
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/* Clear the prior values for input polarity, capture mode. Set the external pin as input */
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reg = base->CHANNEL[channel].SCTRL & (~(TMR_SCTRL_IPS_MASK | TMR_SCTRL_CAPTURE_MODE_MASK | TMR_SCTRL_OEN_MASK));
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/* Set the new values */
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reg |= (TMR_SCTRL_IPS(inputPolarity) | TMR_SCTRL_CAPTURE_MODE(captureMode));
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base->CHANNEL[channel].SCTRL = reg;
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/* Setup if counter should reload when a capture occurs */
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if (reloadOnCapture)
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{
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base->CHANNEL[channel].CSCTRL |= TMR_CSCTRL_ROC_MASK;
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}
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else
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{
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base->CHANNEL[channel].CSCTRL &= ~TMR_CSCTRL_ROC_MASK;
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}
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}
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void QTMR_EnableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
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{
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uint16_t reg;
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reg = base->CHANNEL[channel].SCTRL;
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/* Compare interrupt */
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if (mask & kQTMR_CompareInterruptEnable)
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{
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reg |= TMR_SCTRL_TCFIE_MASK;
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}
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/* Overflow interrupt */
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if (mask & kQTMR_OverflowInterruptEnable)
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{
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reg |= TMR_SCTRL_TOFIE_MASK;
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}
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/* Input edge interrupt */
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if (mask & kQTMR_EdgeInterruptEnable)
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{
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/* Restriction: Do not set both SCTRL[IEFIE] and DMA[IEFDE] */
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base->CHANNEL[channel].DMA &= ~TMR_DMA_IEFDE_MASK;
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reg |= TMR_SCTRL_IEFIE_MASK;
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}
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base->CHANNEL[channel].SCTRL = reg;
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reg = base->CHANNEL[channel].CSCTRL;
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/* Compare 1 interrupt */
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if (mask & kQTMR_Compare1InterruptEnable)
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{
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reg |= TMR_CSCTRL_TCF1EN_MASK;
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}
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/* Compare 2 interrupt */
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if (mask & kQTMR_Compare2InterruptEnable)
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{
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reg |= TMR_CSCTRL_TCF2EN_MASK;
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}
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base->CHANNEL[channel].CSCTRL = reg;
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}
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void QTMR_DisableInterrupts(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
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{
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uint16_t reg;
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reg = base->CHANNEL[channel].SCTRL;
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/* Compare interrupt */
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if (mask & kQTMR_CompareInterruptEnable)
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{
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reg &= ~TMR_SCTRL_TCFIE_MASK;
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}
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/* Overflow interrupt */
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if (mask & kQTMR_OverflowInterruptEnable)
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{
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reg &= ~TMR_SCTRL_TOFIE_MASK;
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}
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/* Input edge interrupt */
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if (mask & kQTMR_EdgeInterruptEnable)
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{
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reg &= ~TMR_SCTRL_IEFIE_MASK;
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}
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base->CHANNEL[channel].SCTRL = reg;
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reg = base->CHANNEL[channel].CSCTRL;
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/* Compare 1 interrupt */
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if (mask & kQTMR_Compare1InterruptEnable)
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{
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reg &= ~TMR_CSCTRL_TCF1EN_MASK;
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}
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/* Compare 2 interrupt */
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if (mask & kQTMR_Compare2InterruptEnable)
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{
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reg &= ~TMR_CSCTRL_TCF2EN_MASK;
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}
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base->CHANNEL[channel].CSCTRL = reg;
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}
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uint32_t QTMR_GetEnabledInterrupts(TMR_Type *base, qtmr_channel_selection_t channel)
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{
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uint32_t enabledInterrupts = 0;
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uint16_t reg;
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reg = base->CHANNEL[channel].SCTRL;
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/* Compare interrupt */
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if (reg & TMR_SCTRL_TCFIE_MASK)
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{
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enabledInterrupts |= kQTMR_CompareFlag;
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}
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/* Overflow interrupt */
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if (reg & TMR_SCTRL_TOFIE_MASK)
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{
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enabledInterrupts |= kQTMR_OverflowInterruptEnable;
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}
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/* Input edge interrupt */
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if (reg & TMR_SCTRL_IEFIE_MASK)
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{
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enabledInterrupts |= kQTMR_EdgeInterruptEnable;
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}
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reg = base->CHANNEL[channel].CSCTRL;
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/* Compare 1 interrupt */
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if (reg & TMR_CSCTRL_TCF1EN_MASK)
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{
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enabledInterrupts |= kQTMR_Compare1InterruptEnable;
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}
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/* Compare 2 interrupt */
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if (reg & TMR_CSCTRL_TCF2EN_MASK)
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{
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enabledInterrupts |= kQTMR_Compare2InterruptEnable;
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}
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return enabledInterrupts;
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}
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uint32_t QTMR_GetStatus(TMR_Type *base, qtmr_channel_selection_t channel)
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{
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uint32_t statusFlags = 0;
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uint16_t reg;
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reg = base->CHANNEL[channel].SCTRL;
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/* Timer compare flag */
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if (reg & TMR_SCTRL_TCF_MASK)
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{
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statusFlags |= kQTMR_CompareFlag;
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}
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/* Timer overflow flag */
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if (reg & TMR_SCTRL_TOF_MASK)
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{
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statusFlags |= kQTMR_OverflowFlag;
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}
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/* Input edge flag */
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if (reg & TMR_SCTRL_IEF_MASK)
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{
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statusFlags |= kQTMR_EdgeFlag;
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}
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reg = base->CHANNEL[channel].CSCTRL;
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/* Compare 1 flag */
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if (reg & TMR_CSCTRL_TCF1_MASK)
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{
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statusFlags |= kQTMR_Compare1Flag;
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}
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/* Compare 2 flag */
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if (reg & TMR_CSCTRL_TCF2_MASK)
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{
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statusFlags |= kQTMR_Compare2Flag;
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}
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return statusFlags;
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}
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void QTMR_ClearStatusFlags(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
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{
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uint16_t reg;
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reg = base->CHANNEL[channel].SCTRL;
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/* Timer compare flag */
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if (mask & kQTMR_CompareFlag)
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{
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reg &= ~TMR_SCTRL_TCF_MASK;
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}
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/* Timer overflow flag */
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if (mask & kQTMR_OverflowFlag)
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{
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reg &= ~TMR_SCTRL_TOF_MASK;
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}
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/* Input edge flag */
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if (mask & kQTMR_EdgeFlag)
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{
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reg &= ~TMR_SCTRL_IEF_MASK;
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}
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base->CHANNEL[channel].SCTRL = reg;
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reg = base->CHANNEL[channel].CSCTRL;
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/* Compare 1 flag */
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if (mask & kQTMR_Compare1Flag)
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{
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reg &= ~TMR_CSCTRL_TCF1_MASK;
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}
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/* Compare 2 flag */
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if (mask & kQTMR_Compare2Flag)
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{
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reg &= ~TMR_CSCTRL_TCF2_MASK;
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}
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base->CHANNEL[channel].CSCTRL = reg;
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}
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void QTMR_SetTimerPeriod(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t ticks)
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{
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/* Set the length bit to reinitialize the counters on a match */
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base->CHANNEL[channel].CTRL |= TMR_CTRL_LENGTH_MASK;
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if (base->CHANNEL[channel].CTRL & TMR_CTRL_DIR_MASK)
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{
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/* Counting down */
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base->CHANNEL[channel].COMP2 = ticks;
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}
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else
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{
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/* Counting up */
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base->CHANNEL[channel].COMP1 = ticks;
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}
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}
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void QTMR_EnableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
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{
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uint16_t reg;
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reg = base->CHANNEL[channel].DMA;
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/* Input Edge Flag DMA Enable */
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if (mask & kQTMR_InputEdgeFlagDmaEnable)
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{
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/* Restriction: Do not set both DMA[IEFDE] and SCTRL[IEFIE] */
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base->CHANNEL[channel].SCTRL &= ~TMR_SCTRL_IEFIE_MASK;
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reg |= TMR_DMA_IEFDE_MASK;
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}
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/* Comparator Preload Register 1 DMA Enable */
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if (mask & kQTMR_ComparatorPreload1DmaEnable)
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{
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reg |= TMR_DMA_CMPLD1DE_MASK;
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}
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/* Comparator Preload Register 2 DMA Enable */
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if (mask & kQTMR_ComparatorPreload2DmaEnable)
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{
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reg |= TMR_DMA_CMPLD2DE_MASK;
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}
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base->CHANNEL[channel].DMA = reg;
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}
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void QTMR_DisableDma(TMR_Type *base, qtmr_channel_selection_t channel, uint32_t mask)
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{
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uint16_t reg;
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reg = base->CHANNEL[channel].DMA;
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/* Input Edge Flag DMA Enable */
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if (mask & kQTMR_InputEdgeFlagDmaEnable)
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{
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reg &= ~TMR_DMA_IEFDE_MASK;
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}
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/* Comparator Preload Register 1 DMA Enable */
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if (mask & kQTMR_ComparatorPreload1DmaEnable)
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{
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reg &= ~TMR_DMA_CMPLD1DE_MASK;
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}
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/* Comparator Preload Register 2 DMA Enable */
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if (mask & kQTMR_ComparatorPreload2DmaEnable)
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{
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reg &= ~TMR_DMA_CMPLD2DE_MASK;
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}
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base->CHANNEL[channel].DMA = reg;
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}
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