161 lines
4.2 KiB
C
161 lines
4.2 KiB
C
/*
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* Copyright (C) 2022, Xiaohua Semiconductor Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2022-04-28 CDT first version
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*/
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#include "board.h"
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/* unlock/lock peripheral */
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#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \
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LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM)
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#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM)
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/**
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* @brief This function is executed in case of error occurrence.
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* @param None
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* @retval None
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*/
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void Error_Handler(void)
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{
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/* USER CODE BEGIN Error_Handler */
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/* User can add his own implementation to report the HAL error return state */
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while (1)
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{
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}
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/* USER CODE END Error_Handler */
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}
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/** System Clock Configuration
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*/
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void SystemClock_Config(void)
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{
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stc_clock_xtal_init_t stcXtalInit;
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stc_clock_pll_init_t stcPLLHInit;
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/* PCLK0, HCLK Max 240MHz */
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/* PCLK1, PCLK4 Max 120MHz */
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/* PCLK2, PCLK3 Max 60MHz */
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/* EX BUS Max 120MHz */
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CLK_SetClockDiv(CLK_BUS_CLK_ALL, \
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(CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \
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CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \
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CLK_HCLK_DIV1));
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(void)CLK_XtalStructInit(&stcXtalInit);
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/* Config Xtal and enable Xtal */
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stcXtalInit.u8Mode = CLK_XTAL_MD_OSC;
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stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW;
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stcXtalInit.u8State = CLK_XTAL_ON;
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stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS;
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(void)CLK_XtalInit(&stcXtalInit);
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(void)CLK_PLLStructInit(&stcPLLHInit);
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/* VCO = (8/1)*120 = 960MHz*/
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stcPLLHInit.u8PLLState = CLK_PLL_ON;
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stcPLLHInit.PLLCFGR = 0UL;
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stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL;
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stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL;
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(void)CLK_PLLInit(&stcPLLHInit);
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/* Highspeed SRAM set to 0 Read/Write wait cycle */
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SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0);
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/* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */
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SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1);
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/* 0-wait @ 40MHz */
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(void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5);
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/* 4 cycles for 200 ~ 250MHz */
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GPIO_SetReadWaitCycle(GPIO_RD_WAIT4);
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CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL);
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}
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/*******************************************************************************
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* Function Name : SysTick_Configuration
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* Description : Configures the SysTick for OS tick.
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* Input : None
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* Output : None
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* Return : None
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*******************************************************************************/
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void SysTick_Configuration(void)
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{
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stc_clock_freq_t stcClkFreq;
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rt_uint32_t cnts;
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CLK_GetClockFreq(&stcClkFreq);
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cnts = (rt_uint32_t)stcClkFreq.u32HclkFreq / RT_TICK_PER_SECOND;
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SysTick_Config(cnts);
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}
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/**
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* This is the timer interrupt service routine.
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*
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*/
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void SysTick_Handler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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/**
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* This function will initial GD32 board.
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*/
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void rt_hw_board_init()
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{
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/* Peripheral registers write unprotected */
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LL_PERIPH_WE(EXAMPLE_PERIPH_WE);
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SystemClock_Config();
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/* Configure the SysTick */
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SysTick_Configuration();
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/* Heap initialization */
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#if defined(RT_USING_HEAP)
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rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
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#endif
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/* Board underlying hardware initialization */
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#ifdef RT_USING_COMPONENTS_INIT
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rt_components_board_init();
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#endif
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#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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}
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void rt_hw_us_delay(rt_uint32_t us)
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{
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uint32_t start, now, delta, reload, us_tick;
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start = SysTick->VAL;
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reload = SysTick->LOAD;
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us_tick = SystemCoreClock / 1000000UL;
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do
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{
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now = SysTick->VAL;
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delta = start > now ? start - now : reload + start - now;
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}
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while (delta < us_tick * us);
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}
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/*@}*/
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