236 lines
8.4 KiB
C
236 lines
8.4 KiB
C
/*
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** ###################################################################
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** Processors: MIMXRT1052CVJ5B
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** MIMXRT1052CVL5B
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** MIMXRT1052DVJ6B
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** MIMXRT1052DVL6B
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**
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** Compilers: Freescale C/C++ for Embedded ARM
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** GNU C Compiler
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** IAR ANSI C/C++ Compiler for ARM
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** Keil ARM C/C++ Compiler
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** MCUXpresso Compiler
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**
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** Reference manual: IMXRT1050RM Rev.2.1, 12/2018
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** Version: rev. 1.2, 2018-11-27
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** Build: b181205
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**
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** Abstract:
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** Provides a system configuration function and a global variable that
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** contains the system frequency. It configures the device and initializes
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** the oscillator (PLL) that is part of the microcontroller device.
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**
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** Copyright 2016 Freescale Semiconductor, Inc.
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** Copyright 2016-2018 NXP
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** All rights reserved.
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**
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** SPDX-License-Identifier: BSD-3-Clause
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**
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** http: www.nxp.com
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** mail: support@nxp.com
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**
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** Revisions:
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** - rev. 0.1 (2017-01-10)
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** Initial version.
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** - rev. 1.0 (2018-09-21)
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** Update interrupt vector table and dma request source.
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** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
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** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
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** - rev. 1.1 (2018-11-16)
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** Update header files to align with IMXRT1050RM Rev.1.
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** - rev. 1.2 (2018-11-27)
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** Update header files to align with IMXRT1050RM Rev.2.1.
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**
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** ###################################################################
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*/
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/*!
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* @file MIMXRT1052
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* @version 1.2
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* @date 2018-11-27
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* @brief Device specific configuration file for MIMXRT1052 (implementation file)
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*
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* Provides a system configuration function and a global variable that contains
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* the system frequency. It configures the device and initializes the oscillator
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* (PLL) that is part of the microcontroller device.
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*/
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#include <stdint.h>
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#include "fsl_device_registers.h"
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/* ----------------------------------------------------------------------------
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-- Core clock
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---------------------------------------------------------------------------- */
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uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
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/* ----------------------------------------------------------------------------
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-- SystemInit()
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---------------------------------------------------------------------------- */
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void SystemInit (void) {
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#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
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SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
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#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
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#if defined(__MCUXPRESSO)
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extern uint32_t g_pfnVectors[]; // Vector table defined in startup code
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SCB->VTOR = (uint32_t)g_pfnVectors;
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#endif
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/* Disable Watchdog Power Down Counter */
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WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK;
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WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK;
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/* Watchdog disable */
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#if (DISABLE_WDOG)
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if (WDOG1->WCR & WDOG_WCR_WDE_MASK)
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{
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WDOG1->WCR &= ~WDOG_WCR_WDE_MASK;
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}
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if (WDOG2->WCR & WDOG_WCR_WDE_MASK)
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{
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WDOG2->WCR &= ~WDOG_WCR_WDE_MASK;
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}
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RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
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RTWDOG->TOVAL = 0xFFFF;
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RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
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#endif /* (DISABLE_WDOG) */
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/* Disable Systick which might be enabled by bootrom */
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if (SysTick->CTRL & SysTick_CTRL_ENABLE_Msk)
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{
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SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
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}
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/* Enable instruction and data caches */
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#if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
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if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
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SCB_EnableICache();
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}
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#endif
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#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT
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if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) {
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SCB_EnableDCache();
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}
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#endif
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SystemInitHook();
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}
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/* ----------------------------------------------------------------------------
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-- SystemCoreClockUpdate()
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---------------------------------------------------------------------------- */
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void SystemCoreClockUpdate (void) {
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uint32_t freq;
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uint32_t PLL1MainClock;
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uint32_t PLL2MainClock;
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/* Periph_clk2_clk ---> Periph_clk */
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if (CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
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{
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switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
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{
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/* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
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case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
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if(CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
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{
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freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ?
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CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
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}
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else
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{
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freq = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U));
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}
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break;
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/* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
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case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
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freq = CPU_XTAL_CLK_HZ;
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break;
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case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
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freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
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CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
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case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
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default:
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freq = 0U;
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break;
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}
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freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
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}
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/* Pre_Periph_clk ---> Periph_clk */
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else
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{
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/* check if pll is bypassed */
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if(CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
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{
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PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ?
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CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
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}
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else
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{
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PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
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CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
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}
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/* check if pll is bypassed */
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if(CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
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{
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PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
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CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
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}
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else
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{
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PLL2MainClock = (CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) ? 22U : 20U));
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}
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PLL2MainClock += ((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM));
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switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
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{
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/* PLL2 ---> Pre_Periph_clk ---> Periph_clk */
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case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
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freq = PLL2MainClock;
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break;
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/* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */
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case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
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freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U;
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break;
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/* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */
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case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
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freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U;
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break;
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/* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */
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case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
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freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
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break;
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default:
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freq = 0U;
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break;
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}
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}
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SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
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}
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/* ----------------------------------------------------------------------------
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-- SystemInitHook()
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---------------------------------------------------------------------------- */
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__attribute__ ((weak)) void SystemInitHook (void) {
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/* Void implementation of the weak function. */
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}
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