412 lines
10 KiB
C
412 lines
10 KiB
C
/*
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* File : drv_pl041.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2017, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2018-05-25 RT-Thread the first version
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*/
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#include <rtthread.h>
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#include <rthw.h>
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#include "drv_pl041.h"
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#include "drv_ac97.h"
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#include "realview.h"
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#define DBG_ENABLE
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#define DBG_SECTION_NAME "PL041"
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// #define DBG_LEVEL DBG_LOG
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// #define DBG_LEVEL DBG_INFO
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#define DBG_LEVEL DBG_WARNING
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// #define DBG_LEVEL DBG_ERROR
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#define DBG_COLOR
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#include <rtdbg.h>
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#define FRAME_PERIOD_US (50)
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#define PL041_CHANNLE_NUM (4)
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#define PL041_READ(_a) (*(volatile rt_uint32_t *)(_a))
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#define PL041_WRITE(_a, _v) (*(volatile rt_uint32_t *)(_a) = (_v))
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struct pl041_irq_def
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{
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pl041_irq_fun_t fun;
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void *user_data;
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};
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static struct pl041_irq_def irq_tbl[PL041_CHANNLE_NUM];
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static void aaci_pl041_delay(rt_uint32_t us)
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{
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volatile int i;
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for (i = us * 10; i != 0; i--);
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}
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static void aaci_ac97_select_codec(void)
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{
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rt_uint32_t v, maincr;
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maincr = AACI_MAINCR_SCRA(0) | AACI_MAINCR_IE | AACI_MAINCR_SL1RXEN | \
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AACI_MAINCR_SL1TXEN | AACI_MAINCR_SL2RXEN | AACI_MAINCR_SL2TXEN;
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v = PL041_READ(&PL041->slfr);
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if (v & AACI_SLFR_2RXV)
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{
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PL041_READ(&PL041->sl2rx);
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}
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if (v & AACI_SLFR_1RXV)
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{
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PL041_READ(&PL041->sl1rx);
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}
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if (maincr != PL041_READ(&PL041->maincr))
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{
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PL041_WRITE(&PL041->maincr, maincr);
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aaci_pl041_delay(1);
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}
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}
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void aaci_ac97_write(rt_uint16_t reg, rt_uint16_t val)
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{
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rt_uint32_t v, timeout;
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aaci_ac97_select_codec();
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PL041_WRITE(&PL041->sl2tx, val << 4);
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PL041_WRITE(&PL041->sl1tx, reg << 12);
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aaci_pl041_delay(FRAME_PERIOD_US);
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timeout = FRAME_PERIOD_US * 8;
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do
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{
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aaci_pl041_delay(1);
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v = PL041_READ(&PL041->slfr);
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}
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while ((v & (AACI_SLFR_1TXB | AACI_SLFR_2TXB)) && --timeout);
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if (v & (AACI_SLFR_1TXB | AACI_SLFR_2TXB))
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{
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LOG_E("timeout waiting for write to complete");
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}
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}
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rt_uint16_t aaci_ac97_read(rt_uint16_t reg)
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{
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rt_uint32_t v, timeout, retries = 10;
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aaci_ac97_select_codec();
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PL041_WRITE(&PL041->sl1tx, (reg << 12) | (1 << 19));
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aaci_pl041_delay(FRAME_PERIOD_US);
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timeout = FRAME_PERIOD_US * 8;
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do
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{
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aaci_pl041_delay(1);
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v = PL041_READ(&PL041->slfr);
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}
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while ((v & AACI_SLFR_1TXB) && --timeout);
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if (v & AACI_SLFR_1TXB)
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{
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LOG_E("timeout on slot 1 TX busy");
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v = ~0x0;
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return v;
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}
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aaci_pl041_delay(FRAME_PERIOD_US);
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timeout = FRAME_PERIOD_US * 8;
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do
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{
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aaci_pl041_delay(1);
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v = PL041_READ(&PL041->slfr) & (AACI_SLFR_1RXV | AACI_SLFR_2RXV);
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}
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while ((v != (AACI_SLFR_1RXV | AACI_SLFR_2RXV)) && --timeout);
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if (v != (AACI_SLFR_1RXV | AACI_SLFR_2RXV))
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{
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LOG_E("timeout on RX valid");
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v = ~0x0;
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return v;
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}
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do
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{
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v = PL041_READ(&PL041->sl1rx) >> 12;
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if (v == reg)
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{
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v = PL041_READ(&PL041->sl2rx) >> 4;
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break;
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}
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else if (--retries)
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{
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LOG_E("ac97 read back fail. retry");
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continue;
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}
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else
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{
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LOG_E("wrong ac97 register read back (%x != %x)", v, reg);
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v = ~0x0;
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}
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}
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while (retries);
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return v;
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}
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int aaci_pl041_channle_disable(int channle)
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{
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rt_uint32_t v;
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void *p_rx, *p_tx;
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p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14);
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p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14);
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v = PL041_READ(p_rx);
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v &= ~AACI_CR_EN;
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PL041_WRITE(p_rx, v);
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v = PL041_READ(p_tx);
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v &= ~AACI_CR_EN;
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PL041_WRITE(p_tx, v);
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return 0;
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}
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int aaci_pl041_channle_enable(int channle)
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{
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rt_uint32_t v;
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void *p_rx, *p_tx;
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p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14);
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p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14);
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v = PL041_READ(p_rx);
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v |= AACI_CR_EN;
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PL041_WRITE(p_rx, v);
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v = PL041_READ(p_tx);
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v |= AACI_CR_EN;
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PL041_WRITE(p_tx, v);
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return 0;
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}
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int aaci_pl041_channle_read(int channle, rt_uint16_t *buff, int count)
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{
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void *p_data, *p_status;
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int i = 0;
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p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14);
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p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channle * 0x20);
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for (i = 0; (!(PL041_READ(p_status) & AACI_SR_RXFE)) && (i < count); i++)
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{
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buff[i] = (rt_uint16_t)PL041_READ(p_data);
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}
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return i;
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}
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int aaci_pl041_channle_write(int channle, rt_uint16_t *buff, int count)
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{
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void *p_data, *p_status;
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int i = 0;
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p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14);
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p_data = (void *)((rt_uint32_t)(&(PL041->dr1[0])) + channle * 0x20);
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for (i = 0; (!(PL041_READ(p_status) & AACI_SR_TXFF)) && (i < count); i++)
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{
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PL041_WRITE(p_data, buff[i]);
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}
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return i;
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}
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int aaci_pl041_channle_cfg(int channle, pl041_cfg_t cgf)
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{
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rt_uint32_t v;
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void *p_rx, *p_tx;
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p_rx = (void *)((rt_uint32_t)(&PL041->rxcr1) + channle * 0x14);
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p_tx = (void *)((rt_uint32_t)(&PL041->txcr1) + channle * 0x14);
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v = AACI_CR_FEN | AACI_CR_SZ16 | cgf->itype;
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PL041_WRITE(p_rx, v);
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v = AACI_CR_FEN | AACI_CR_SZ16 | cgf->otype;
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PL041_WRITE(p_tx, v);
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ac97_set_vol(cgf->vol);
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ac97_set_rate(cgf->rate);
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return 0;
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}
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void aaci_pl041_irq_enable(int channle, rt_uint32_t vector)
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{
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rt_uint32_t v;
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void *p_irq;
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vector &= vector & 0x7f;
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p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channle * 0x14);
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v = PL041_READ(p_irq);
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v |= vector;
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PL041_WRITE(p_irq, v);
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}
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void aaci_pl041_irq_disable(int channle, rt_uint32_t vector)
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{
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rt_uint32_t v;
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void *p_irq;
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vector &= vector & 0x7f;
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p_irq = (void *)((rt_uint32_t)(&PL041->iie1) + channle * 0x14);
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v = PL041_READ(p_irq);
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v &= ~vector;
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PL041_WRITE(p_irq, v);
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}
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rt_err_t aaci_pl041_irq_register(int channle, pl041_irq_fun_t fun, void *user_data)
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{
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if (channle < 0 || channle >= PL041_CHANNLE_NUM)
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{
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LOG_E("%s channle:%d err.", __FUNCTION__, channle);
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return -RT_ERROR;
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}
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irq_tbl[channle].fun = fun;
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irq_tbl[channle].user_data = user_data;
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return RT_EOK;
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}
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rt_err_t aaci_pl041_irq_unregister(int channle)
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{
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if (channle < 0 || channle >= PL041_CHANNLE_NUM)
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{
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LOG_E("%s channle:%d err.", __FUNCTION__, channle);
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return -RT_ERROR;
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}
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irq_tbl[channle].fun = RT_NULL;
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irq_tbl[channle].user_data = RT_NULL;
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return RT_EOK;
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}
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static void aaci_pl041_irq_handle(int irqno, void *param)
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{
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rt_uint32_t mask, channle, m;
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struct pl041_irq_def *_irq = param;
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void *p_status;
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mask = PL041_READ(&PL041->allints);
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PL041_WRITE(PL041->intclr, mask);
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for (channle = 0; (channle < PL041_CHANNLE_NUM) && (mask); channle++)
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{
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mask = mask >> 7;
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m = mask & 0x7f;
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if (m & AACI_ISR_ORINTR)
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{
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LOG_W("RX overrun on chan %d", channle);
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}
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if (m & AACI_ISR_RXTOINTR)
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{
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LOG_W("RX timeout on chan %d", channle);
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}
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if (mask & AACI_ISR_URINTR)
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{
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LOG_W("TX underrun on chan %d", channle);
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}
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p_status = (void *)((rt_uint32_t)(&PL041->sr1) + channle * 0x14);
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if (_irq[channle].fun != RT_NULL)
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{
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_irq[channle].fun(PL041_READ(p_status), _irq[channle].user_data);
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}
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}
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}
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rt_err_t aaci_pl041_init(void)
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{
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rt_uint32_t i, maincr;
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maincr = AACI_MAINCR_SCRA(0) | AACI_MAINCR_IE | AACI_MAINCR_SL1RXEN | \
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AACI_MAINCR_SL1TXEN | AACI_MAINCR_SL2RXEN | AACI_MAINCR_SL2TXEN;
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for (i = 0; i < 4; i++)
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{
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void *base = (void *)((rt_uint32_t)(&PL041->rxcr1) + i * 0x14);
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PL041_WRITE(base + AACI_IE, 0);
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PL041_WRITE(base + AACI_TXCR, 0);
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PL041_WRITE(base + AACI_RXCR, 0);
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}
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PL041_WRITE(&PL041->intclr, 0x1fff);
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PL041_WRITE(&PL041->maincr, maincr);
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PL041_WRITE(&PL041->reset, 0);
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aaci_pl041_delay(2);
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PL041_WRITE(&PL041->reset, RESET_NRST);
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rt_hw_interrupt_install(43, aaci_pl041_irq_handle, &irq_tbl, "aaci_pl041");
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rt_hw_interrupt_umask(43);
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return 0;
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}
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#if 0
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#define PL041_DUMP(_v) rt_kprintf("%32s:addr:0x%08x data:0x%08x\n", #_v, &(_v), (_v))
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int _aaci_pl041_reg_dump(int argc, char **argv)
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{
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PL041_DUMP(PL041->rxcr1);
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PL041_DUMP(PL041->txcr1);
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PL041_DUMP(PL041->sr1);
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PL041_DUMP(PL041->isr1);
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PL041_DUMP(PL041->iie1);
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PL041_DUMP(PL041->rxcr2);
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PL041_DUMP(PL041->txcr2);
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PL041_DUMP(PL041->sr2);
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PL041_DUMP(PL041->isr2);
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PL041_DUMP(PL041->iie2);
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PL041_DUMP(PL041->rxcr3);
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PL041_DUMP(PL041->txcr3);
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PL041_DUMP(PL041->sr3);
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PL041_DUMP(PL041->isr3);
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PL041_DUMP(PL041->iie3);
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PL041_DUMP(PL041->rxcr4);
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PL041_DUMP(PL041->txcr4);
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PL041_DUMP(PL041->sr4);
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PL041_DUMP(PL041->isr4);
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PL041_DUMP(PL041->iie4);
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PL041_DUMP(PL041->sl1rx);
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PL041_DUMP(PL041->sl1tx);
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PL041_DUMP(PL041->sl2rx);
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PL041_DUMP(PL041->sl2tx);
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PL041_DUMP(PL041->sl12rx);
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PL041_DUMP(PL041->sl12tx);
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PL041_DUMP(PL041->slfr);
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PL041_DUMP(PL041->slistat);
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PL041_DUMP(PL041->slien);
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PL041_DUMP(PL041->intclr);
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PL041_DUMP(PL041->maincr);
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PL041_DUMP(PL041->reset);
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PL041_DUMP(PL041->sync);
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PL041_DUMP(PL041->allints);
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PL041_DUMP(PL041->mainfr);
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PL041_DUMP(PL041->dr1[0]);
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PL041_DUMP(PL041->dr2[0]);
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PL041_DUMP(PL041->dr3[0]);
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PL041_DUMP(PL041->dr4[0]);
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return 0;
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}
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FINSH_FUNCTION_EXPORT_ALIAS(_aaci_pl041_reg_dump, __cmd_pl041_dump, aaci pl041 dump reg.);
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#endif
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