491 lines
18 KiB
C
491 lines
18 KiB
C
/*
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* The Clear BSD License
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* Copyright (c) 2017, NXP
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* All rights reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted (subject to the limitations in the disclaimer below) provided
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* that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __FSL_DCDC_H__
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#define __FSL_DCDC_H__
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#include "fsl_common.h"
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/*!
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* @addtogroup dcdc
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief DCDC driver version. */
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#define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
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/*!
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* @brief DCDC status flags.
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*/
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enum _dcdc_status_flags_t
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{
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kDCDC_LockedOKStatus = (1U << 0U), /*!< Indicate DCDC status. 1'b1: DCDC already settled 1'b0: DCDC is settling. */
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};
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/*!
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* @brief The current bias of low power comparator.
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*/
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typedef enum _dcdc_comparator_current_bias
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{
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kDCDC_ComparatorCurrentBias50nA = 0U, /*!< The current bias of low power comparator is 50nA. */
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kDCDC_ComparatorCurrentBias100nA = 1U, /*!< The current bias of low power comparator is 100nA. */
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kDCDC_ComparatorCurrentBias200nA = 2U, /*!< The current bias of low power comparator is 200nA. */
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kDCDC_ComparatorCurrentBias400nA = 3U, /*!< The current bias of low power comparator is 400nA. */
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} dcdc_comparator_current_bias_t;
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/*!
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* @brief The threshold of over current detection.
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*/
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typedef enum _dcdc_over_current_threshold
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{
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kDCDC_OverCurrentThresholdAlt0 = 0U, /*!< 1A in the run mode, 0.25A in the power save mode. */
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kDCDC_OverCurrentThresholdAlt1 = 1U, /*!< 2A in the run mode, 0.25A in the power save mode. */
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kDCDC_OverCurrentThresholdAlt2 = 2U, /*!< 1A in the run mode, 0.2A in the power save mode. */
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kDCDC_OverCurrentThresholdAlt3 = 3U, /*!< 2A in the run mode, 0.2A in the power save mode. */
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} dcdc_over_current_threshold_t;
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/*!
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* @brief The threshold if peak current detection.
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*/
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typedef enum _dcdc_peak_current_threshold
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{
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kDCDC_PeakCurrentThresholdAlt0 = 0U, /*!< 150mA peak current threshold. */
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kDCDC_PeakCurrentThresholdAlt1 = 1U, /*!< 250mA peak current threshold. */
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kDCDC_PeakCurrentThresholdAlt2 = 2U, /*!< 350mA peak current threshold. */
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kDCDC_PeakCurrentThresholdAlt3 = 3U, /*!< 450mA peak current threshold. */
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kDCDC_PeakCurrentThresholdAlt4 = 4U, /*!< 550mA peak current threshold. */
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kDCDC_PeakCurrentThresholdAlt5 = 5U, /*!< 650mA peak current threshold. */
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} dcdc_peak_current_threshold_t;
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/*!
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* @brief The period of counting the charging times in power save mode.
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*/
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typedef enum _dcdc_count_charging_time_period
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{
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kDCDC_CountChargingTimePeriod8Cycle = 0U, /*!< Eight 32k cycle. */
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kDCDC_CountChargingTimePeriod16Cycle = 1U, /*!< Sixteen 32k cycle. */
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} dcdc_count_charging_time_period_t;
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/*!
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* @brief The threshold of the counting number of charging times
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*/
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typedef enum _dcdc_count_charging_time_threshold
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{
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kDCDC_CountChargingTimeThreshold32 = 0U, /*!< 0x0: 32. */
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kDCDC_CountChargingTimeThreshold64 = 1U, /*!< 0x1: 64. */
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kDCDC_CountChargingTimeThreshold16 = 2U, /*!< 0x2: 16. */
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kDCDC_CountChargingTimeThreshold8 = 3U, /*!< 0x3: 8. */
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} dcdc_count_charging_time_threshold_t;
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/*!
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* @brief Oscillator clock option.
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*/
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typedef enum _dcdc_clock_source
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{
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kDCDC_ClockAutoSwitch = 0U, /*!< Automatic clock switch from internal oscillator to external clock. */
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kDCDC_ClockInternalOsc = 1U, /*!< Use internal oscillator. */
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kDCDC_ClockExternalOsc = 2U, /*!< Use external 24M crystal oscillator. */
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} dcdc_clock_source_t;
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/*!
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* @brief Configuration for DCDC detection.
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*/
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typedef struct _dcdc_detection_config
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{
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bool enableXtalokDetection; /*!< Enable xtalok detection circuit. */
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bool powerDownOverVoltageDetection; /*!< Power down over-voltage detection comparator. */
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bool powerDownLowVlotageDetection; /*!< Power down low-voltage detection comparator. */
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bool powerDownOverCurrentDetection; /*!< Power down over-current detection. */
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bool powerDownPeakCurrentDetection; /*!< Power down peak-current detection. */
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bool powerDownZeroCrossDetection; /*!< Power down the zero cross detection function for discontinuous conductor
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mode. */
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dcdc_over_current_threshold_t OverCurrentThreshold; /*!< The threshold of over current detection. */
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dcdc_peak_current_threshold_t PeakCurrentThreshold; /*!< The threshold of peak current detection. */
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} dcdc_detection_config_t;
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/*!
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* @brief Configuration for the loop control.
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*/
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typedef struct _dcdc_loop_control_config
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{
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bool enableCommonHysteresis; /*!< Enable hysteresis in switching converter common mode analog comparators.
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This feature will improve transient supply ripple and efficiency. */
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bool enableCommonThresholdDetection; /*!< Increase the threshold detection for common mode analog comparator. */
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bool enableInvertHysteresisSign; /*!< Invert the sign of the hysteresis in DC-DC analog comparators. */
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bool enableRCThresholdDetection; /*!< Increase the threshold detection for RC scale circuit. */
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uint32_t enableRCScaleCircuit; /*!< Available range is 0~7. Enable analog circuit of DC-DC converter to respond
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faster under transient load conditions. */
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uint32_t complementFeedForwardStep; /*!< Available range is 0~7. Two's complement feed forward step in duty cycle in
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the switching DC-DC converter. Each time this field makes a transition from
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0x0, the loop filter of the DC-DC converter is stepped once by a value
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proportional to the change. This can be used to force a certain control loop
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behavior, such as improving response under known heavy load transients. */
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uint32_t controlParameterMagnitude; /*!< Available range is 0~15. Magnitude of proportional control parameter in the
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switching DC-DC converter control loop. */
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uint32_t integralProportionalRatio; /*!< Available range is 0~3.Ratio of integral control parameter to proportional
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control parameter in the switching DC-DC converter, and can be used to
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optimize efficiency and loop response. */
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} dcdc_loop_control_config_t;
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/*!
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* @brief Configuration for DCDC low power.
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*/
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typedef struct _dcdc_low_power_config
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{
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bool enableOverloadDetection; /*!< Enable the overload detection in power save mode, if current is larger than the
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overloading threshold (typical value is 50 mA), DCDC will switch to the run mode
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automatically. */
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bool enableAdjustHystereticValue; /*!< Adjust hysteretic value in low power from 12.5mV to 25mV. */
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dcdc_count_charging_time_period_t
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countChargingTimePeriod; /*!< The period of counting the charging times in power save mode. */
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dcdc_count_charging_time_threshold_t
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countChargingTimeThreshold; /*!< the threshold of the counting number of charging times during
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the period that lp_overload_freq_sel sets in power save mode. */
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} dcdc_low_power_config_t;
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/*!
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* @brief Configuration for DCDC internal regulator.
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*/
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typedef struct _dcdc_internal_regulator_config
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{
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bool enableLoadResistor; /*!< control the load resistor of the internal regulator of DCDC, the load resistor is
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connected as default "true", and need set to "false" to disconnect the load
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resistor. */
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uint32_t feedbackPoint; /*!< Available range is 0~3. Select the feedback point of the internal regulator. */
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} dcdc_internal_regulator_config_t;
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/*!
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* @brief Configuration for min power setting.
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*/
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typedef struct _dcdc_min_power_config
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{
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bool enableUseHalfFreqForContinuous; /*!< Set DCDC clock to half frequency for the continuous mode. */
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} dcdc_min_power_config_t;
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*******************************************************************************
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* API
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******************************************************************************/
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/*!
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* @name Initialization and deinitialization
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* @{
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*/
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/*!
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* @brief Enable the access to DCDC registers.
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*
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* @param base DCDC peripheral base address.
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*/
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void DCDC_Init(DCDC_Type *base);
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/*!
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* @brief Disable the access to DCDC registers.
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*
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* @param base DCDC peripheral base address.
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*/
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void DCDC_Deinit(DCDC_Type *base);
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/* @} */
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/*!
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* @name Status
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* @{
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*/
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/*!
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* @brief Get DCDC status flags.
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*
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* @param base peripheral base address.
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* @return Mask of asserted status flags. See to "_dcdc_status_flags_t".
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*/
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uint32_t DCDC_GetstatusFlags(DCDC_Type *base);
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/* @} */
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/*!
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* @name Misc control.
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* @{
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*/
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/*!
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* @brief Enable the output range comparator.
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*
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* The output range comparator is disabled by default.
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*
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* @param base DCDC peripheral base address.
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* @param enable Enable the feature or not.
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*/
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static inline void DCDC_EnableOutputRangeComparator(DCDC_Type *base, bool enable)
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{
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if (enable)
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{
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base->REG0 &= ~DCDC_REG0_PWD_CMP_OFFSET_MASK;
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}
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else
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{
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base->REG0 |= DCDC_REG0_PWD_CMP_OFFSET_MASK;
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}
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}
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/*!
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* @brief Configure the DCDC clock source.
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*
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* @param base DCDC peripheral base address.
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* @param clockSource Clock source for DCDC. See to "dcdc_clock_source_t".
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*/
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void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource);
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/*!
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* @brief Get the default setting for detection configuration.
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*
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* The default configuration are set according to responding registers' setting when powered on.
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* They are:
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* @code
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* config->enableXtalokDetection = false;
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* config->powerDownOverVoltageDetection = true;
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* config->powerDownLowVlotageDetection = false;
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* config->powerDownOverCurrentDetection = true;
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* config->powerDownPeakCurrentDetection = true;
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* config->powerDownZeroCrossDetection = true;
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* config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0;
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* config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0;
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* @endcode
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*
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* @param config Pointer to configuration structure. See to "dcdc_detection_config_t"
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*/
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void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config);
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/*!
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* @breif Configure the DCDC detection.
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*
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* @param base DCDC peripheral base address.
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* @param config Pointer to configuration structure. See to "dcdc_detection_config_t"
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*/
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void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config);
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/*!
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* @brief Get the default setting for low power configuration.
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*
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* The default configuration are set according to responding registers' setting when powered on.
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* They are:
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* @code
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* config->enableOverloadDetection = true;
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* config->enableAdjustHystereticValue = false;
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* config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle;
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* config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32;
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* @endcode
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*
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* @param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
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*/
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void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config);
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/*!
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* @brief Configure the DCDC low power.
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*
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* @param base DCDC peripheral base address.
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* @param config Pointer to configuration structure. See to "dcdc_low_power_config_t".
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*/
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void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config);
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/*!
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* @brief Reset current alert signal. Alert signal is generate by peak current detection.
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*
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* @param base DCDC peripheral base address.
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* @param enable Switcher to reset signal. True means reset signal. False means don't reset signal.
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*/
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void DCDC_ResetCurrentAlertSignal(DCDC_Type *base, bool enable);
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/*!
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* @brief Set the bangap trim value to trim bandgap voltage.
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*
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* @param base DCDC peripheral base address.
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* @param TrimValue The bangap trim value. Available range is 0U-31U.
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*/
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static inline void DCDC_SetBandgapVoltageTrimValue(DCDC_Type *base, uint32_t trimValue)
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{
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base->REG1 &= ~DCDC_REG1_VBG_TRIM_MASK;
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base->REG1 |= DCDC_REG1_VBG_TRIM(trimValue);
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}
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/*!
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* @brief Get the default setting for loop control configuration.
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*
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* The default configuration are set according to responding registers' setting when powered on.
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* They are:
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* @code
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* config->enableCommonHysteresis = false;
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* config->enableCommonThresholdDetection = false;
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* config->enableInvertHysteresisSign = false;
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* config->enableRCThresholdDetection = false;
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* config->enableRCScaleCircuit = 0U;
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* config->complementFeedForwardStep = 0U;
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* config->controlParameterMagnitude = 2U;
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* config->integralProportionalRatio = 2U;
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* @endcode
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*
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* @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t"
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*/
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void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config);
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/*!
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* @brief Configure the DCDC loop control.
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*
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* @param base DCDC peripheral base address.
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* @param config Pointer to configuration structure. See to "dcdc_loop_control_config_t".
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*/
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void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config);
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/*!
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* @brief Configure for the min power.
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*
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* @param base DCDC peripheral base address.
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* @param config Pointer to configuration structure. See to "dcdc_min_power_config_t".
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*/
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void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config);
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/*!
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* @brief Set the current bias of low power comparator.
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*
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* @param base DCDC peripheral base address.
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* @param biasVaule The current bias of low power comparator. Refer to "dcdc_comparator_current_bias_t".
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*/
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static inline void DCDC_SetLPComparatorBiasValue(DCDC_Type *base, dcdc_comparator_current_bias_t biasVaule)
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{
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base->REG1 &= ~DCDC_REG1_LP_CMP_ISRC_SEL_MASK;
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base->REG1 |= DCDC_REG1_LP_CMP_ISRC_SEL(biasVaule);
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}
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static inline void DCDC_LockTargetVoltage(DCDC_Type *base)
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{
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base->REG3 |= DCDC_REG3_DISABLE_STEP_MASK;
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}
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/*!
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* @brief Adjust the target voltage of VDD_SOC in run mode and low power mode.
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*
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* This function is to adjust the target voltage of DCDC output. Change them and finally wait until the output is
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* stabled.
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* Set the target value of run mode the same as low power mode before entering power save mode, because DCDC will switch
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* back to run mode if it detects the current loading is larger than about 50 mA(typical value).
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*
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* @param base DCDC peripheral base address.
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* @param VDDRun Target value in run mode. 25 mV each step from 0x00 to 0x1F. 00 is for 0.8V, 0x1F is for 1.575V.
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* @param VDDStandby Target value in low power mode. 25 mV each step from 0x00 to 0x4. 00 is for 0.9V, 0x4 is for 1.0V.
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*/
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void DCDC_AdjustTargetVoltage(DCDC_Type *base, uint32_t VDDRun, uint32_t VDDStandby);
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/*!
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* @brief Configure the DCDC internal regulator.
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*
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* @param base DCDC peripheral base address.
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* @param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t".
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*/
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void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config);
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/*!
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* @brief Ajust delay to reduce ground noise.
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*
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* @param base DCDC peripheral base address.
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* @param enable Enable the feature or not.
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*/
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static inline void DCDC_EnableAdjustDelay(DCDC_Type *base, bool enable)
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{
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if (enable)
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{
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base->REG3 |= DCDC_REG3_MISC_DELAY_TIMING_MASK;
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}
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else
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{
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base->REG3 &= ~DCDC_REG3_MISC_DELAY_TIMING_MASK;
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}
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}
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/*!
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* @brief Enable/Disable to improve the transition from heavy load to light load. It is valid while zero
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* cross detection is enabled. If ouput exceeds the threshold, DCDC would return CCM from DCM.
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*
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* @param base DCDC peripheral base address.
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* @param enable Enable the feature or not.
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*/
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static inline void DCDC_EnableImproveTransition(DCDC_Type *base, bool enable)
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{
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if (enable)
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{
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base->REG2 |= DCDC_REG2_DCM_SET_CTRL_MASK;
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}
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else
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{
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base->REG2 &= ~DCDC_REG2_DCM_SET_CTRL_MASK;
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}
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}
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/* @} */
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/*!
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* @name Application guideline.
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* @{
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*/
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/*!
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* @brief Boot DCDC into DCM(discontinous conduction mode).
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*
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* pwd_zcd=0x0;
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* pwd_cmp_offset=0x0;
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* dcdc_loopctrl_en_rcscale=0x3 or 0x5;
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* DCM_set_ctrl=1'b1;
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*
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* @param base DCDC peripheral base address.
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*/
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void DCDC_BootIntoDCM(DCDC_Type *base);
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/*!
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* @brief Boot DCDC into CCM(continous conduction mode).
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*
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* pwd_zcd=0x1;
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* pwd_cmp_offset=0x0;
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* dcdc_loopctrl_en_rcscale=0x3;
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*
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* @param base DCDC peripheral base address.
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*/
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void DCDC_BootIntoCCM(DCDC_Type *base);
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#if defined(__cplusplus)
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}
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#endif
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|
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#endif /* __FSL_DCDC_H__ */
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