212 lines
7.5 KiB
C
212 lines
7.5 KiB
C
/*
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* Copyright 2019-2020 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_OCOTP_H_
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#define _FSL_OCOTP_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup ocotp
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* @{
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*/
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/*******************************************************************************
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* Definitions
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*******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief OCOTP driver version. */
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#define FSL_OCOTP_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
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/*@}*/
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#ifndef OCOTP_READ_FUSE_DATA_COUNT
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#define OCOTP_READ_FUSE_DATA_COUNT (1U)
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#endif
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/*! @brief _ocotp_status Error codes for the OCOTP driver. */
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enum
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{
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kStatus_OCOTP_AccessError = MAKE_STATUS(kStatusGroup_SDK_OCOTP, 0), /*!< eFuse and shadow register access error. */
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kStatus_OCOTP_CrcFail = MAKE_STATUS(kStatusGroup_SDK_OCOTP, 1), /*!< CRC check failed. */
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kStatus_OCOTP_ReloadError =
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MAKE_STATUS(kStatusGroup_SDK_OCOTP, 2), /*!< Error happens during reload shadow register. */
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kStatus_OCOTP_ProgramFail = MAKE_STATUS(kStatusGroup_SDK_OCOTP, 3), /*!< Fuse programming failed. */
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kStatus_OCOTP_Locked = MAKE_STATUS(kStatusGroup_SDK_OCOTP, 4), /*!< Fuse is locked and cannot be programmed. */
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};
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#if (defined(FSL_FEATURE_OCOTP_HAS_TIMING_CTRL) && FSL_FEATURE_OCOTP_HAS_TIMING_CTRL)
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/*! @brief OCOTP timing structure.
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* Note that, these value are used for calcalating the read/write timings.
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* And the values should statisfy below rules:
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*
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* Tsp_rd=(WAIT+1)/ipg_clk_freq should be >= 150ns;
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* Tsp_pgm=(RELAX+1)/ipg_clk_freq should be >= 100ns;
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* Trd = ((STROBE_READ+1)- 2*(RELAX_READ+1)) /ipg_clk_freq,
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* The Trd is required to be larger than 40 ns.
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* Tpgm = ((STROBE_PROG+1)- 2*(RELAX_PROG+1)) /ipg_clk_freq;
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* The Tpgm should be configured within the range of 9000 ns < Tpgm < 11000 ns;
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*/
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typedef struct _ocotp_timing
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{
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uint32_t wait; /*!< Wait time value to fill in the TIMING register. */
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uint32_t relax; /*!< Relax time value to fill in the TIMING register. */
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uint32_t strobe_prog; /*!< Storbe program time value to fill in the TIMING register. */
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uint32_t strobe_read; /*!< Storbe read time value to fill in the TIMING register. */
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} ocotp_timing_t;
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#endif /* FSL_FEATURE_OCOTP_HAS_TIMING_CTRL */
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/*******************************************************************************
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* API
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*******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @brief Initializes OCOTP controller.
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*
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* @param base OCOTP peripheral base address.
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* @param srcClock_Hz source clock frequency in unit of Hz. When the macro
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* FSL_FEATURE_OCOTP_HAS_TIMING_CTRL is defined as 0, this parameter is not used,
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* application could pass in 0 in this case.
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*/
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void OCOTP_Init(OCOTP_Type *base, uint32_t srcClock_Hz);
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/*!
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* @brief De-initializes OCOTP controller.
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*
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* @retval kStatus_Success upon successful execution, error status otherwise.
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*/
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void OCOTP_Deinit(OCOTP_Type *base);
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/*!
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* @brief Checking the BUSY bit in CTRL register.
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* Checking this BUSY bit will help confirm if the OCOTP controller is ready for access.
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*
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* @param base OCOTP peripheral base address.
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* @retval true for bit set and false for cleared.
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*/
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static inline bool OCOTP_CheckBusyStatus(OCOTP_Type *base)
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{
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return ((OCOTP_CTRL_BUSY_MASK == (base->CTRL & OCOTP_CTRL_BUSY_MASK)) ? (true) : (false));
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}
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/*!
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* @brief Checking the ERROR bit in CTRL register.
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*
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* @param base OCOTP peripheral base address.
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* @retval true for bit set and false for cleared.
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*/
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static inline bool OCOTP_CheckErrorStatus(OCOTP_Type *base)
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{
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return ((OCOTP_CTRL_ERROR_MASK == (base->CTRL & OCOTP_CTRL_ERROR_MASK)) ? (true) : (false));
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}
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/*!
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* @brief Clear the error bit if this bit is set.
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*
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* @param base OCOTP peripheral base address.
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*/
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static inline void OCOTP_ClearErrorStatus(OCOTP_Type *base)
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{
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base->CTRL_CLR = OCOTP_CTRL_CLR_ERROR_MASK;
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}
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/*!
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* @brief Reload the shadow register.
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* This function will help reload the shadow register without reseting the OCOTP module.
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* Please make sure the OCOTP has been initialized before calling this API.
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*
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* @param base OCOTP peripheral base addess.
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* @retval kStatus_Success Reload success.
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* @retval kStatus_OCOTP_ReloadError Reload failed.
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*/
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status_t OCOTP_ReloadShadowRegister(OCOTP_Type *base);
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/*!
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* @brief Read the fuse shadow register with the fuse addess.
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*
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* @deprecated Use @ref OCOTP_ReadFuseShadowRegisterExt instead of this function.
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*
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* @param base OCOTP peripheral base address.
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* @param address the fuse address to be read from.
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* @return The read out data.
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*/
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uint32_t OCOTP_ReadFuseShadowRegister(OCOTP_Type *base, uint32_t address);
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/*!
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* @brief Read the fuse shadow register from the fuse addess.
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*
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* This function reads fuse from @p address, how many words to read is specified
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* by the parameter @p fuseWords. This function could read at most
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* OCOTP_READ_FUSE_DATA_COUNT fuse word one time.
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*
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* @param base OCOTP peripheral base address.
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* @param address the fuse address to be read from.
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* @param data Data array to save the readout fuse value.
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* @param fuseWords How many words to read.
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* @retval kStatus_Success Read success.
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* @retval kStatus_Fail Error occurs during read.
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*/
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status_t OCOTP_ReadFuseShadowRegisterExt(OCOTP_Type *base, uint32_t address, uint32_t *data, uint8_t fuseWords);
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/*!
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* @brief Write the fuse shadow register with the fuse addess and data.
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* Please make sure the wrtie address is not locked while calling this API.
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*
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* @param base OCOTP peripheral base address.
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* @param address the fuse address to be written.
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* @param data the value will be writen to fuse address.
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* @retval write status, kStatus_Success for success and kStatus_Fail for failed.
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*/
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status_t OCOTP_WriteFuseShadowRegister(OCOTP_Type *base, uint32_t address, uint32_t data);
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/*!
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* @brief Write the fuse shadow register and lock it.
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*
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* Please make sure the wrtie address is not locked while calling this API.
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*
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* Some OCOTP controller supports ECC mode and redundancy mode (see reference mananual
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* for more details). OCOTP controller will auto select ECC or redundancy
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* mode to program the fuse word according to fuse map definition. In ECC mode, the
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* 32 fuse bits in one word can only be written once. In redundancy mode, the word can
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* be written more than once as long as they are different fuse bits. Set parameter
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* @p lock as true to force use ECC mode.
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*
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* @param base OCOTP peripheral base address.
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* @param address The fuse address to be written.
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* @param data The value will be writen to fuse address.
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* @param lock Lock or unlock write fuse shadow register operation.
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* @retval kStatus_Success Program and reload success.
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* @retval kStatus_OCOTP_Locked The eFuse word is locked and cannot be programmed.
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* @retval kStatus_OCOTP_ProgramFail eFuse word programming failed.
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* @retval kStatus_OCOTP_ReloadError eFuse word programming success, but
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* error happens during reload the values.
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* @retval kStatus_OCOTP_AccessError Cannot access eFuse word.
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*/
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status_t OCOTP_WriteFuseShadowRegisterWithLock(OCOTP_Type *base, uint32_t address, uint32_t data, bool lock);
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/*!
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* @brief Get the OCOTP controller version from the register.
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*
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* @param base OCOTP peripheral base address.
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* @retval return the version value.
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*/
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static inline uint32_t OCOTP_GetVersion(OCOTP_Type *base)
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{
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return (base->VERSION);
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}
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#if defined(__cplusplus)
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}
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#endif
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/*! @}*/
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#endif /* _FSL_OCOTP_H_ */
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