341 lines
11 KiB
C
341 lines
11 KiB
C
/*
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* Copyright 2016-2021 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_CACHE_H_
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#define _FSL_CACHE_H_
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#include "fsl_common.h"
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/*!
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* @addtogroup cache_lmem
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @name Driver version */
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/*@{*/
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/*! @brief cache driver version. */
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#define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 6))
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/*@}*/
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/*! @brief code bus cache line size is equal to system bus line size, so the unified I/D cache line size equals too. */
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#define L1CODEBUSCACHE_LINESIZE_BYTE \
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FSL_FEATURE_L1ICACHE_LINESIZE_BYTE /*!< The code bus CACHE line size is 16B = 128b. */
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#define L1SYSTEMBUSCACHE_LINESIZE_BYTE \
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L1CODEBUSCACHE_LINESIZE_BYTE /*!< The system bus CACHE line size is 16B = 128b. */
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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#if (FSL_FEATURE_SOC_LMEM_COUNT == 1)
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/*!
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* @name cache control for L1 cache (local memory controller for code/system bus cache)
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*@{
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*/
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/*!
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* @brief Enables the processor code bus cache.
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*
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*/
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void L1CACHE_EnableCodeCache(void);
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/*!
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* @brief Disables the processor code bus cache.
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*
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*/
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void L1CACHE_DisableCodeCache(void);
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/*!
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* @brief Invalidates the processor code bus cache.
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*
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*/
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void L1CACHE_InvalidateCodeCache(void);
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/*!
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* @brief Invalidates processor code bus cache by range.
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*
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* @param address The physical address of cache.
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* @param size_byte size of the memory to be invalidated.
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* @note Address and size should be aligned to "L1CODCACHE_LINESIZE_BYTE".
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* The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
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* startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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void L1CACHE_InvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte);
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/*!
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* @brief Cleans the processor code bus cache.
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*
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*/
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void L1CACHE_CleanCodeCache(void);
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/*!
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* @brief Cleans processor code bus cache by range.
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*
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* @param address The physical address of cache.
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* @param size_byte size of the memory to be cleaned.
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* @note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE".
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* The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
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* startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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void L1CACHE_CleanCodeCacheByRange(uint32_t address, uint32_t size_byte);
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/*!
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* @brief Cleans and invalidates the processor code bus cache.
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*
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*/
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void L1CACHE_CleanInvalidateCodeCache(void);
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/*!
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* @brief Cleans and invalidate processor code bus cache by range.
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*
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* @param address The physical address of cache.
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* @param size_byte size of the memory to be Cleaned and Invalidated.
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* @note Address and size should be aligned to "L1CODEBUSCACHE_LINESIZE_BYTE".
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* The startAddr here will be forced to align to L1CODEBUSCACHE_LINESIZE_BYTE if
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* startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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void L1CACHE_CleanInvalidateCodeCacheByRange(uint32_t address, uint32_t size_byte);
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/*!
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* @brief Enables/disables the processor code bus write buffer.
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*
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* @param enable The enable or disable flag.
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* true - enable the code bus write buffer.
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* false - disable the code bus write buffer.
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*/
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static inline void L1CACHE_EnableCodeCacheWriteBuffer(bool enable)
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{
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if (enable)
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{
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LMEM->PCCCR |= LMEM_PCCCR_ENWRBUF_MASK;
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}
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else
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{
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LMEM->PCCCR &= ~LMEM_PCCCR_ENWRBUF_MASK;
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}
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}
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#if defined(FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE) && FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE
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/*!
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* @brief Enables the processor system bus cache.
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*
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*/
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void L1CACHE_EnableSystemCache(void);
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/*!
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* @brief Disables the processor system bus cache.
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*
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*/
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void L1CACHE_DisableSystemCache(void);
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/*!
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* @brief Invalidates the processor system bus cache.
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*
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*/
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void L1CACHE_InvalidateSystemCache(void);
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/*!
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* @brief Invalidates processor system bus cache by range.
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*
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* @param address The physical address of cache.
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* @param size_byte size of the memory to be invalidated.
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* @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
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* The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
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* startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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void L1CACHE_InvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte);
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/*!
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* @brief Cleans the processor system bus cache.
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*
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*/
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void L1CACHE_CleanSystemCache(void);
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/*!
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* @brief Cleans processor system bus cache by range.
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*
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* @param address The physical address of cache.
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* @param size_byte size of the memory to be cleaned.
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* @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
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* The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
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* startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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void L1CACHE_CleanSystemCacheByRange(uint32_t address, uint32_t size_byte);
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/*!
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* @brief Cleans and invalidates the processor system bus cache.
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*
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*/
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void L1CACHE_CleanInvalidateSystemCache(void);
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/*!
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* @brief Cleans and Invalidates processor system bus cache by range.
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*
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* @param address The physical address of cache.
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* @param size_byte size of the memory to be Clean and Invalidated.
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* @note Address and size should be aligned to "L1SYSTEMBUSCACHE_LINESIZE_BYTE".
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* The startAddr here will be forced to align to L1SYSTEMBUSCACHE_LINESIZE_BYTE if
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* startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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void L1CACHE_CleanInvalidateSystemCacheByRange(uint32_t address, uint32_t size_byte);
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/*!
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* @brief Enables/disables the processor system bus write buffer.
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*
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* @param enable The enable or disable flag.
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* true - enable the code bus write buffer.
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* false - disable the code bus write buffer.
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*/
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static inline void L1CACHE_EnableSystemCacheWriteBuffer(bool enable)
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{
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if (enable)
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{
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LMEM->PSCCR |= LMEM_PSCCR_ENWRBUF_MASK;
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}
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else
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{
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LMEM->PSCCR &= ~LMEM_PSCCR_ENWRBUF_MASK;
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}
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}
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/*@}*/
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#endif /* FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE */
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/*!
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* @name cache control for unified L1 cache driver
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*@{
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*/
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/*!
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* @brief Invalidates cortex-m4 L1 instrument cache by range.
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*
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* @param address The start address of the memory to be invalidated.
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* @param size_byte The memory size.
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* @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
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*/
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void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte);
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/*!
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* @brief Invalidates cortex-m4 L1 data cache by range.
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*
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* @param address The start address of the memory to be invalidated.
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* @param size_byte The memory size.
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* @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
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*/
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static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
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{
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L1CACHE_InvalidateICacheByRange(address, size_byte);
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}
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/*!
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* @brief Cleans cortex-m4 L1 data cache by range.
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*
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* @param address The start address of the memory to be cleaned.
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* @param size_byte The memory size.
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* @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
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*/
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void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte);
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/*!
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* @brief Cleans and Invalidates cortex-m4 L1 data cache by range.
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*
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* @param address The start address of the memory to be clean and invalidated.
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* @param size_byte The memory size.
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* @note The start address and size_byte should be 16-Byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
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*/
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void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte);
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/*@}*/
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#endif /* FSL_FEATURE_SOC_LMEM_COUNT == 1 */
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/*!
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* @name Unified Cache Control for all caches
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*@{
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*/
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/*!
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* @brief Invalidates instruction cache by range.
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*
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* @param address The physical address.
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* @param size_byte size of the memory to be invalidated.
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* @note Address and size should be aligned to 16-Byte due to the cache operation unit
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* FSL_FEATURE_L1ICACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
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* size if startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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static inline void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
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{
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L1CACHE_InvalidateICacheByRange(address, size_byte);
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}
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/*!
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* @brief Invalidates data cache by range.
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*
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* @param address The physical address.
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* @param size_byte size of the memory to be invalidated.
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* @note Address and size should be aligned to 16-Byte due to the cache operation unit
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* FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
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* size if startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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static inline void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
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{
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L1CACHE_InvalidateDCacheByRange(address, size_byte);
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}
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/*!
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* @brief Clean data cache by range.
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*
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* @param address The physical address.
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* @param size_byte size of the memory to be cleaned.
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* @note Address and size should be aligned to 16-Byte due to the cache operation unit
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* FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
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* size if startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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static inline void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
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{
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L1CACHE_CleanDCacheByRange(address, size_byte);
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}
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/*!
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* @brief Cleans and Invalidates data cache by range.
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*
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* @param address The physical address.
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* @param size_byte size of the memory to be Cleaned and Invalidated.
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* @note Address and size should be aligned to 16-Byte due to the cache operation unit
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* FSL_FEATURE_L1DCACHE_LINESIZE_BYTE. The startAddr here will be forced to align to the cache line
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* size if startAddr is not aligned. For the size_byte, application should make sure the
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* alignment or make sure the right operation order if the size_byte is not aligned.
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*/
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static inline void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
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{
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L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
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}
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/*@}*/
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#if defined(__cplusplus)
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}
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#endif
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/*! @}*/
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#endif /* _FSL_CACHE_H_*/
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