133 lines
4.9 KiB
C
133 lines
4.9 KiB
C
/*
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* Change Logs:
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* Date Author Notes
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* 2021-04-20 liuhy the first version
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*
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* Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*/
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#ifndef __ES_CONF_INFO_SPI_H__
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#define __ES_CONF_INFO_SPI_H__
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#include "es_conf_info_map.h"
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#include <ald_spi.h>
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#include <ald_gpio.h>
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#include <ald_cmu.h>
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/* SPI 配置 */
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#define SPI_BUS_CONFIG(_CONF_,_I_) do{_CONF_.mode = 0U; \
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_CONF_.mode |= ( ES_SPI##_I_##_MASTER_SLAVE | \
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ES_SPI##_I_##_WIRE_3_4 | \
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ES_SPI##_I_##_CPHA_1_2 | \
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ES_SPI##_I_##_CPOL_H_L | \
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ES_SPI##_I_##_CS | \
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ES_SPI##_I_##_M_L_SB ); \
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_CONF_.data_width = ES_SPI##_I_##_DATA_W; \
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_CONF_.max_hz = ES_SPI##_I_##_MAX_HZ; \
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}while(0)
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// spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */
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// spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */
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// spi_config.mode |= RT_SPI_CPHA; /* 第二边沿采样 */
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// spi_config.mode |= RT_SPI_CPOL; /* 空闲高电平 */
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// spi_config.mode |= RT_SPI_NO_CS; /* 禁用软件从机选择管理 */
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// spi_config.mode |= RT_SPI_MSB; /* 高位在前 */
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// spi_config.data_width = 8; /* 数据长度：8 */
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// spi_config.max_hz = 2000000; /* 最快时钟频率 */
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#define ES_C_SPI_CLK_POL_HIGH RT_SPI_CPOL
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#define ES_C_SPI_CLK_POL_LOW !RT_SPI_CPOL
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#define ES_C_SPI_CLK_PHA_FIRST !RT_SPI_CPHA
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#define ES_C_SPI_CLK_PHA_SECOND RT_SPI_CPHA
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#define ES_C_SPI_MSB RT_SPI_MSB
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#define ES_C_SPI_LSB RT_SPI_LSB
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#define ES_C_SPI_CS_LOW_LEVEL 0
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#define ES_C_SPI_CS_HIGH_LEVEL 1
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/* codes_main */
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#ifndef ES_DEVICE_NAME_SPI0_BUS
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#define ES_DEVICE_NAME_SPI0_BUS "spi0"
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#endif
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#ifndef ES_DEVICE_NAME_SPI0_DEV0
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#define ES_DEVICE_NAME_SPI0_DEV0 "spi00"
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#endif
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#ifndef ES_DEVICE_NAME_SPI1_BUS
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#define ES_DEVICE_NAME_SPI1_BUS "spi1"
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#endif
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#ifndef ES_DEVICE_NAME_SPI1_DEV0
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#define ES_DEVICE_NAME_SPI1_DEV0 "spi10"
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#endif
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#define ES_SPI_CS_LEVEL ES_C_SPI_CS_LOW_LEVEL
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#ifndef ES_SPI0_CPHA_1_2
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#define ES_SPI0_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND
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#endif
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#ifndef ES_SPI0_CPOL_H_L
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#define ES_SPI0_CPOL_H_L ES_C_SPI_CLK_POL_HIGH
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#endif
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#ifndef ES_SPI0_M_L_SB
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#define ES_SPI0_M_L_SB RT_SPI_MSB
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#endif
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#ifndef ES_SPI0_MAX_HZ
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#define ES_SPI0_MAX_HZ 2000000
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#endif
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#ifndef ES_SPI0_NSS_PIN
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#define ES_SPI0_NSS_PIN 0xFFFFFFFF
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#endif
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#ifndef ES_SPI1_CPHA_1_2
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#define ES_SPI1_CPHA_1_2 ES_C_SPI_CLK_PHA_SECOND
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#endif
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#ifndef ES_SPI1_CPOL_H_L
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#define ES_SPI1_CPOL_H_L ES_C_SPI_CLK_POL_HIGH
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#endif
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#ifndef ES_SPI1_M_L_SB
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#define ES_SPI1_M_L_SB RT_SPI_MSB
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#endif
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#ifndef ES_SPI1_MAX_HZ
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#define ES_SPI1_MAX_HZ 2000000
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#endif
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#ifndef ES_SPI1_NSS_PIN
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#define ES_SPI1_NSS_PIN 0xFFFFFFFF
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#endif
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#define ES_SPI0_MASTER_SLAVE !RT_SPI_SLAVE
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#define ES_SPI0_WIRE_3_4 !RT_SPI_3WIRE
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#define ES_SPI0_CS RT_SPI_NO_CS
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#define ES_SPI0_DATA_W 8
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#define ES_SPI1_MASTER_SLAVE !RT_SPI_SLAVE
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#define ES_SPI1_WIRE_3_4 !RT_SPI_3WIRE
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#define ES_SPI1_CS RT_SPI_NO_CS
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#define ES_SPI1_DATA_W 8
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#endif
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